PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 271
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PEF20550HV21XT
Manufacturer Part Number
PEF20550HV21XT
Description
Manufacturer
Lantiq
Datasheet
1.PEF20550HV21XT.pdf
(407 pages)
Specifications of PEF20550HV21XT
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 271 of 407
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W:MAAR
W:MACR
Downstream: CFI port 1, timeslot 7, bits 7 … 0 from PCM port 0, timeslot 0, bits 7 … 0
W:MADR
W:MAAR
W:MACR
The following sequence sets transmit timeslot 0 of PCM port 0 to high impedance:
W:MADR
W:MAAR
W:MACR
Example
In PCM mode 0 and CFI mode 0 the following non-transparent CFI to CFI loop via PCM
port 0, timeslot 0 shall be programmed:
Upstream: CFI port 2, timeslot 4, bits 7 … 0 to PCM port 0, timeslot 0, bits 7 … 0
W:MADR
Semiconductor Group
= 1000 0000
= 1001 0100
= 0111 0001
= 1000 0000
= 0001 1011
= 0111 0001
= 0000 0000
= 1000 0000
= 0110 0000
B
B
B
B
B
B
B
B
B
PCM timeslot encoding (pointer to upstream DM)
CFI timeslot encoding (address of upstream CM)
CM code for switching a 64 kBit/s/bits 7 … 0
channel (0001)
PCM timeslot encoding (pointer to upstream DM)
CFI timeslot encoding (address of downstream CM)
CM code for switching a 64 kBit/s/bits 7 … 0
channel (0001)
all bits to high Z
PCM timeslot encoding
MOC code to access the tristate field
271
Application Hints
PEB 20550
PEF 20550
01.96
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