PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 22
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PEF20550HV21XT
Manufacturer Part Number
PEF20550HV21XT
Description
Manufacturer
Lantiq
Datasheet
1.PEF20550HV21XT.pdf
(407 pages)
Specifications of PEF20550HV21XT
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Pin Definitions and Functions (cont’d)
Boundary Scan Interface, according to IEEE Std. 1149.1
Pin No.
76
75
74
73
Note: Pin 75 (TDI) and pin 76 (TMS) are internally connected to
Semiconductor Group
Symbol
TMS
TDI
TDO
TCK
Input (I)
Output (O)
I
(internal
pull-up)
(internal
pull-up)
O
I
I
Function
Test Mode Select
A 0 -> 1 transition on this pin is required to step
through the TAP-controller state machine.
Test Data Input
In the appropriate TAP-controller state test data or
a instruction is shifted in via this line
Test Data Output
In the appropriate TAP-controller state test data or
a instruction is shifted out via this line.
Test Clock
Single rate test data clock.
22
V
DD
via pull-up resistors.
PEB 20550
PEF 20550
Overview
01.96
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