PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 163

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.7
4.7.1
Access in demultiplexed
Access in multiplexed
Reset value: xx
RD7..0
Interrupt controlled data transfer (interrupt mode, selected if DMA-bit in register
XBCH is reset).
Up to 32 bytes of received data can be read from the RFIFO following an RPF or an RME
interrupt.
RPF-interrupt:
RME-interrupt:
DMA controlled data transfer (DMA-mode, selected if DMA-bit in register XBCH is
set).
If the RFIFO contains 32 bytes, the SACCO autonomously requests a block data transfer
by activating the DRQRA/B-line as long as the 31st read cycle is finished. This forces
the DMA-controller to continuously perform bus cycles until 32 bytes are transferred from
the SACCO to the system memory (DMA-controller mode: demand transfer, level
triggered).
If the RFIFO contains less than 32 bytes (one short frame or the last bytes of a long
frame) the SACCO requests a block data transfer depending on the contents of the
RFIFO according to the following table:
RFIFO Contents (bytes)
(1), 2, 3
4 - 7
8 - 15
16 - 32
Semiconductor Group
bit 7
P-interface mode:
P-interface mode:
RD7
SACCO
Receive FIFO (RFIFO)
Receive Data 7…0, data byte received on the serial interface.
RD6
H
exactly 32 bytes to be read.
the number of bytes can be determined reading the registers
RBCL, RBCH.
RD5
read
read
RD4
address (Ch-A/Ch-B): 00
address: (Ch-A/Ch-B): 00
163
DMA Transfers (bytes)
4
8
16
32
RD3
Detailed Register Description
RD2
H
H
..1F
..3E
RD1
H
H
/40
/80
PEB 20550
PEF 20550
H
H
..5F
bit 0
..BE
RD0
H
H
01.96