PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 329

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 50
Synchronous Transfer Channel Type
CT#2
0
0
0
0
1
1
1
1
ISTA_E:
SOV:
Interrupt Status Register EPIC
The ISTA register should be read after an interrupt in order to determine the interrupt
source. Two maskable (MASK_E) interrupts are provided in connection with the
synchronous transfer utility:
SIN:
Semiconductor Group
bit 7
TIN
CT#1
0
0
1
1
0
0
1
1
Synchronous Transfer Interrupt; The SIN interrupt is enabled if at
least one synchronous transfer channel (A and/or B) is enabled via
the STCR:TAE, TBE bits. The SIN interrupt is generated when the
access window for the P opens. After the occurrence of the SIN
interrupt (logical 1) the P can read and/or write the synchronous
transfer data registers (STDA, STDB). The window where the P can
access the data registers is open for the duration of one frame
(125 s) minus 17 RCL cycles if only one synchronous channel is
enabled and it is open for one frame minus 33 RCL cycles if both A
and B channels are enabled. The SIN bit is reset by reading ISTA_E.
Synchronous Transfer Overflow; The SOV interrupt is generated
(logical 1) if the P fails to access the data registers (STDA, STDB)
within the access window. The SOV bit is reset by reading ISTA_E.
SFI
CT#0
0
1
0
1
0
1
0
1
MFFI
®
Bandwidth
not allowed
64 kBit/s
32 kBit/s
32 kBit/s
16 kBit/s
16 kBit/s
16 kBit/s
16 kBit/s
MAC
329
read/write reset value:
PFI
PIM
Transferred Bits
–
bits 7 … 0
bits 3 … 0
bits 7 … 4
bits 1 … 0
bits 3 … 2
bits 5 … 4
bits 7 … 6
Application Hints
SIN
00
PEB 20550
PEF 20550
H
bit 0
SOV
01.96