PEB20570FV3.1T Infineon Technologies, PEB20570FV3.1T Datasheet - Page 118

• Manufacturer Part Number: PEB20570FV3.1T
• Manufacturer: Infineon Technologies

Specifications of PEB20570FV3.1T

• Lead Free Status / Rohs Status: Not Compliant

Figure 36
4.3.2.6
The IOMU serial data processing is according to the IOM-2 specifications. Incoming
serial data is converted into parallel bytes, and stored in the I-buffer input blocks. The
sequence for every time slot received is from MSB (bit 7) to LSB (bit 0). Transmission is
performed in the opposite direction, from MSB (bit 7) to LSB (bit 0).
4.3.2.7
The data read from the IOMU frame buffers by the DSP always reside in the low byte of
the 16-bit word. The high byte of the read word is driven by the 8-bit IOMU Data Prefix
Register (IDPR). The data prefix is used to accelerate the A-/µ-law to linear conversions
(refer to
Note: Any octet written by the DSP to any location in the IOMU frame buffers should
Data Sheet
FSC
DCL
DD0/1
DU0/1
FSC
DCL
DD0/1
DU0/1
reside in the low byte (8 LSB). The high byte of the written word is “don’t care”.
Chapter
TS31
bit0
IOMU Serial Data Processing
IOMU Parallel Data Processing
TS31
TS31
TS31
bit0
bit0
IOM-2 Interface Timing in Single/Double Clock Mode
bit0
4.5).
Frame Start
Frame Start
TS0
bit7
TS0
bit7
= Upstream Sampling
TS0
bit7
TS0
TS0
bit6
bit7
TS0
bit6
TS0
bit5
TS0
bit5
TS0
bit6
101
TS0
TS0
bit4
bit6
TS0
bit4
Double Data Rate DCL
Single Data Rate DCL
TS0
bit3
TS0
bit3
= FSC Sampling
TS0
bit5
TS0
TS0
bit2
bit5
TS0
bit2
Functional Description
TS0
bit1
TS0
bit1
TS0
bit4
TS0
TS0
bit0
bit4
TS0
bit0
PEB 20570
PEB 20571
2003-07-31
TS1
bit7
TS1
bit7