PEB20570FV3.1T Infineon Technologies, PEB20570FV3.1T Datasheet - Page 227

PEB20570FV3.1T

Manufacturer Part Number
PEB20570FV3.1T
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEB20570FV3.1T

Lead Free Status / Rohs Status
Not Compliant
6.2.6.12 LCLK2 Control Register
LCLK2 Control Register (GLCLK2)
Reset value: 0000
Note: ’x’ = unused bits, read as 0
.
LCLK2EN
LCLK2(1:0) LCLK2 Output Clock Rate
Data Sheet
15
7
x
x
LCLK2 Output Enable
0 =
1 =
Note: This option is valid only when LCLK2 is output. When LCLK2 is
00 =
01 =
10 =
11 =
H
14
x
6
x
input the frequency is determined externally.
LCLK2 is input (default)
LCLK2 is driven outward via LCLK2 pin
2.048 MHz (default)
4.096 MHz
8.192 MHz
16.384 MHz
13
5
x
x
12
4
x
x
read/write
210
11
3
x
x
LCLK2EN
10
x
2
Register Description
Address: D08C
LCLK2(1:0)
9
1
x
PEB 20570
PEB 20571
2003-07-31
8
x
0
H

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