PEB20570FV3.1T Infineon Technologies, PEB20570FV3.1T Datasheet - Page 277

• Manufacturer Part Number: PEB20570FV3.1T
• Manufacturer: Infineon Technologies

Specifications of PEB20570FV3.1T

• Lead Free Status / Rohs Status: Not Compliant

Table 72
Parameter
ALE low before RD X CS falling edge t
ALE hold time after RD X CS rising
edge
ALE pulse width
A-bus setup time before ALE falling
edge
A-bus hold time after ALE falling edge t
RD X CS falling edge to D-bus valid
D-bus float after RD X CS rising edge t
Figure 68
8.6.3
The IREQ (Interrupt REQuest) output signal of the DELIC is activated as a result of a
DSP writing operation to the OCMD register (OAK mailbox command register). Such an
operation sets the OAK mailbox busy bit (OBUSY), which drives directly the IREQ output
signal. The IREQ signal may be masked, by programming the MASK bit within the P-
interface Control Register (UPCR).
The P may force the DELIC to drive the interrupt-vector over the data-bus, by activation
(low) of the interrupt acknowledge input signal (IACK). In Motorola mode an interrupt
acknowledge cycle consists of one IACK pulse, during which the interrupt vector is
issued by the DELIC. In Intel/Infineon mode an interrupt acknowledge cycle consists of
Data Sheet
RDxCS
ALE
AD
Interrupt Acknowledge Cycle Timing
Timing For Read Cycle in Intel/Infineon Multiplexed Mode
Read Cycle in Intel/Infineon Multiplexed Mode
t
WL
Address
t
SAL
Electrical Characteristics and Timing Diagrams
t
HRL
Symbol
t
t
t
t
HRL
HLR
WL
SAL
HAL
DRD
DRDH
t
HA
260
L
min.
5
5
7
12
5
0
0
Limit Values
t
DRD
Data
max.
28
16
Unit
ns
ns
ns
ns
ns
ns
ns
t
DRDH
t
HLR
Notes
Output load
capacity of
50 pF
PEB 20570
PEB 20571
2003-07-31