PEB20570FV3.1T Infineon Technologies, PEB20570FV3.1T Datasheet - Page 136

• Manufacturer Part Number: PEB20570FV3.1T
• Manufacturer: Infineon Technologies

Specifications of PEB20570FV3.1T

• Lead Free Status / Rohs Status: Not Compliant

4.7
4.7.1
Messages are transceived serially, bit by bit over the line and undergo encoding/
decoding according to the HDLC protocol. A received message is collected bit by bit from
the line and stored as octets in the Receive buffer and read by the DSP. A transmitted
message which is placed by the DSP as octets in the Transmit buffer, is transmitted bit
by bit over the line.
The GHDLC (General HDLC) controller works similar to HDLCU (refer to
Overview” on Page
• it has its own physical interface with the following signal lines:
• it works at a speed of up to 8.192 Mbit/s
• it supports also multi master bus
• it may work independently from the internal clocking (FSC, PDC,..) using an external
• the receive/transmit buffer in the GHDLC are 2 x 32 Bytes large, respectively
Like the HDLC Controller, the GHDLC Controller consists also of two parts: a hardware
block (GHDLC Unit for fast events) and a processor (OAK DSP).
Data from the serial input line (LRxD) is processed and stored in the Receive Buffer
which is to be read by the DSP. Transmit data is placed by the DSP in the Transmit
Buffer, is processed by hardware and transmitted over the serial line (LTxD).
.
Figure 46
4.7.2
Each GHDLC channel has three main modes of operation:
• HDLC Mode: In this mode flag-recognition/insertion and zero deletion/addition are
Data Sheet
DSP
Double
Buffer
DSP
Double
Buffer
LRxD, LTxD, LTSC, LCxD, LCLK,
clock
performed. CRC decoding/encoding may be performed.
GHDLC Unit
GHDLC Overview
GHDLC General Modes of Operation
Data Processing in the GHDLC
status and interrupt vector
113). Main features/differences:
Transmit Buffer
Receive Buffer
command vector
set-up vectors
119
Processing
Processing
Transmit
Receive
Functional Description
data out to line
data in from line
bit by bit
bit by bit
PEB 20570
PEB 20571
2003-07-31
“HDLC
LTxD
LRxD