PEB20570FV3.1T Infineon Technologies, PEB20570FV3.1T Datasheet - Page 304

• Manufacturer Part Number: PEB20570FV3.1T
• Manufacturer: Infineon Technologies

Specifications of PEB20570FV3.1T

• Lead Free Status / Rohs Status: Not Compliant

9.4
Figure 98
If the DELIC DSP uses the internal 61.44 MHz clock, the reset value of the DELIC
registers can only be guarantied 200 ns after the rising edge of the reset signal.
If an external DSP clock is used, the reset behaviour is normal, e.g. the reset values are
valid after the falling edge of the reset signal.
In order to guaranty the reset behaviour of the DELIC in any case, the external circuity
as shown in
When reset is deactivated the internal DSP clock is used.
Note: The frequency of the external clock is not important. The higher the frequency the
Data Sheet
faster the reset values are valid. A clock frequency in the range of several MHz
(e.g. 4 MHz) is recommended.
Reset Behaviour
Figure 98
Guaranteed Reset Behaviour
External Clock
is recommended. During reset, the DSP is clocked externally.
287
CLK_DSP
DSP_FRQ
RESET
DELIC-LC/-PB
Application Hints
PEB 20570
PEB 20571
2003-07-31