MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 168

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

State Diagram
Figure 110: Simplified State Diagram
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
ACT = ACTIVE
AREF = AUTO REFRESH
BST = BURST TERMINATE
CKEH = Exit power-down
CKEL = Enter power-down
DPD = Enter deep power-down
applied
Power
WRITE
LMR
PRE
PREALL
Power
PRE
EMR
LMR
WRITE A
on
WRITING
WRITING
power-
Active
down
DPDX = Exit deep power-down
EMR = LOAD EXTENDED MODE REGISTER
LMR = LOAD MODE REGISTER
PRE = PRECHARGE
PREALL = PRECHARGE all banks
READ = READ w/o auto precharge
DPDX
WRITE
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
LMR
CKEL
power-
down
Deep
WRITE A
WRITE A
CKEH
PRE
DPD
Precharging
precharged
all banks
168
active
Row
Idle:
ACT
PRE
SREF
READ A
WRITE
READ
CKEH
refresh
READ A
PRE
Self
SREFX
Micron Technology, Inc. reserves the right to change products or specifications without notice.
SRR
CKEL
READ
Precharge
AREF
power-
down
terminate
READING
READING
BST
Burst
SRR
READ A
READ A = READ w/ auto precharge
SREF = Enter self refresh
SREFX = Exit self refresh
SRR = STATUS REGISTER READ
WRITE = WRITE w/o auto precharge
WRITE A = WRITE w/ auto precharge
refresh
Automatic sequence
Command sequence
Auto
READ
READ
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READ
State Diagram