MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 211

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

SELF REFRESH Operation
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
The SELF REFRESH command can be used to retain data in the device while the rest of
the system is powered down. When in self refresh mode, the device retains data without
external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH
command, except that CKE is disabled (LOW). All command and address input signals
except CKE are “Don’t Care” during self refresh.
During self refresh, the device is refreshed as defined in the extended mode register.
(see Partial-Array Self Refresh (page 177).) An internal temperature sensor adjusts the
refresh rate to optimize device power consumption while ensuring data integrity. (See
Temperature-Compensated Self Refresh (page 176).)
The procedure for exiting self refresh requires a sequence of commands. First, CK must
be stable prior to CKE going HIGH. When CKE is HIGH, the device must have NOP com-
mands issued for
During SELF REFRESH operation, refresh intervals are scheduled internally and may
vary. These refresh intervals may differ from the specified
the SELF REFRESH command must not be used as a substitute for the AUTO REFRESH
command.
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
t
XSR to complete any internal refresh already in progress.
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
SELF REFRESH Operation
t
REFI time. For this reason,
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