MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 189

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

Figure 125: Data Output Timing –
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
DQ[15:8] and UDQS, collectively
DQ (First data no longer valid)
DQ (First data no longer valid)
DQ (First data no longer valid)
DQ (First data no longer valid)
DQ[7:0] and LDQS, collectively
DQ (Last data valid)
DQ (Last data valid)
DQ (Last data valid)
DQ (Last data valid)
Notes:
UDQS
1.
2.
3. DQ transitioning after DQS transitions define the
4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
5.
6. The data valid window is derived for each DQS transitions and is defined as
7. DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, or DQ15.
LDQS
CK#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CK
t
t
with DQS transition and ends with the last valid DQ transition.
er byte and UDQS defines the upper byte.
t
HP is the lesser of
DQSQ is derived at each DQS clock edge and is not cumulative over time and begins
QH is derived from
3
3
4
4
4
4
4
4
4
7
7
7
7
7
7
7
7
4
4
4
7
7
6
6
T1
t
DQSQ,
t HP
1
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
t
QH, and Data Valid Window (x16)
t HP
t
CL or
t
1
t DQSQ
HP:
t QH
t DQSQ
T2
5
t QH
Data valid
t
2
t
QH =
189
window
CH clock transition collectively when a bank is active.
Data valid
5
T2
T2
T2
window
t HP
2
T2
T2
T2
1
t
HP -
t DQSQ
T2n
t QH
t DQSQ
Data valid
t QH
5
window
t
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t HP
QHS.
T2n
Data valid
T2n
T2n
5
window
2
1
T2n
T2n
T2n
T3
t DQSQ
t QH
t DQSQ
t QH
5
t HP
Data valid
2
window
1
Data valid
5
window
T3
t
T3
T3
2
T3
DQSQ window. LDQS defines the low-
T3
T3
T3n
t DQSQ
t DQSQ
t HP
t QH
t QH
1
Data valid
5
5
window
Data valid
2
2
window
T3n
T3n
T4
T3n
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T3n
T3n
T3n
READ Operation
t
QH -
t
DQSQ.