MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 60

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

Column Address Operations
RANDOM DATA READ (05h-E0h)
Figure 35: RANDOM DATA READ (05h-E0h) Operation
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Cycle type
I/O[7:0]
SR[6]
D
Dn
OUT
Dn + 1
D
The column address operations affect how data is input to and output from the cache
registers within the selected die (LUNs). These features provide host flexibility for man-
aging data, especially when the host internal buffer is smaller than the number of data
bytes or words in the cache register.
When the asynchronous interface is active, column address operations can address any
byte in the selected cache register.
The RANDOM DATA READ (05h-E0h) command changes the column address of the se-
lected cache register and enables data output from the last selected die (LUN). This
command is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It
is also accepted by the selected die (LUN) during CACHE READ operations
(RDY = 1; ARDY = 0).
Writing 05h to the command register, followed by two column address cycles contain-
ing the column address, followed by the E0h command, puts the selected die (LUN)
into data output mode. After the E0h command cycle is issued, the host must wait at
least
mode until another valid command is issued.
In devices with more than one die (LUN) per target, during and following interleaved
die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be
issued prior to issuing the RANDOM DATA READ (05h-E0h). In this situation, using the
RANDOM DATA READ (05h-E0h) command without the READ STATUS ENHANCED
(78h) command will result in bus contention because two or more die (LUNs) could
output data.
OUT
t
WHR before requesting data output. The selected die (LUN) stays in data output
t
RHW
Command
05h
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
Address
C1
60
Address
C2
Command
Micron Technology, Inc. reserves the right to change products or specifications without notice.
E0h
t
Column Address Operations
WHR
D
Dk
© 2009 Micron Technology, Inc. All rights reserved.
OUT
Dk + 1
D
OUT
Dk + 2
D
OUT