MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 193

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

Figure 128: Data Input Timing
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Notes:
Data for any WRITE burst can be truncated by a subsequent PRECHARGE command, as
shown in Figure 138 (page 202) and Figure 139 (page 203). Note that only the data-in
pairs that are registered prior to the
any subsequent data-in should be masked with DM, as shown in Figure 138 (page 202)
and Figure 139 (page 203). After the PRECHARGE command, a subsequent command
to the same bank cannot be issued until
DQS
DM
CK#
DQ
CK
1. WRITE command issued at T0.
2.
3.
4. For x16, LDQS controls the lower byte; UDQS controls the upper byte. For x32, DQS0 con-
5. For x16, LDM controls the lower byte; UDM controls the upper byte. For x32, DM0 con-
4
5
t
t
trols DQ[7:0], DQS1 controls DQ[15:8], DQS2 controls DQ[23:16], and DQS3 controls
DQ[31:24].
trols DQ[7:0], DM1 controls DQ[15:8], DM2 controls DQ[23:16], and DM3 controls
DQ[31:24].
DSH (MIN) generally occurs during
DSS (MIN) generally occurs during
t
WPRES
T0
t
1
DQSS
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
t DS
D
T1
b
IN
t
WPRE
t
DSH
t DH
193
T1n
2
t
Transitioning Data
t
DQSL
DSS
t
WR period are written to the internal array, and
3
T2
t
t
DQSS (MAX).
DQSS (MIN).
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
t
t
DQSH
DSH
RP is met.
T2n
2
t
t
WPST
DSS
3
T3
Don’t Care
© 2009 Micron Technology, Inc. All rights reserved.
WRITE Operation