MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 55

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

Table 18: Feature Addresses 01h: Timing Mode
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Subfeature
Parameter
P1
Timing mode
P2
P3
P4
Options
Mode 0
(default)
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Notes:
1. The timing mode feature address is used to change the default timing mode. The timing
2. Supported for both 1.8V and 3.3V.
3. Supported for 3.3V only.
mode should be selected to indicate the maximum speed at which the device will re-
ceive commands, addresses, and data cycles. The five supported settings for the timing
mode are shown. The default timing mode is mode 0. The device returns to mode 0
when the device is power cycled. Supported timing modes are reported in the parame-
ter page.
I/O7
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
I/O6
Reserved (0)
Reserved (0)
Reserved (0)
Reserved (0)
Reserved (0)
Reserved (0)
Reserved (0)
Reserved (0)
Reserved (0)
I/O5
55
I/O4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
I/O3
I/O2
0
0
0
0
1
1
I/O1
0
0
1
1
0
0
Feature Operations
© 2009 Micron Technology, Inc. All rights reserved.
I/O0
0
1
0
1
0
1
Value
00h
01h
01h
01h
01h
01h
00h
00h
00h
Notes
1, 2
2
2
2
2
3