MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 172

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

Standard Mode Register
Figure 113: Standard Mode Register Definition
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Note:
The standard mode register bit definition enables the selection of burst length, burst
type, CAS latency (CL), and operating mode, as shown in Figure 113. Reserved states
should not be used as this may result in setting the device into an unknown state or
cause incompatibility with future versions of LPDDR devices. The standard mode regis-
ter is programmed via the LOAD MODE REGISTER command (with BA0 = 0 and BA1 =
0) and will retain the stored information until it is programmed again, until the device
goes into deep power-down mode, or until the device loses power.
Reprogramming the mode register will not alter the contents of the memory, provided
it is performed correctly. The mode register must be loaded when all banks are idle and
no bursts are in progress, and the controller must wait
quent operation. Violating any of these requirements will result in unspecified operation.
1. The integer n is equal to the most significant address bit.
Mn
0
–
...
M10
M
0
–
n + 2
0
0
1
1
M9
0
–
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
M
M8
n + 1
n + 2
0
1
0
1
0
–
BA1
0
M7
n + 1
0
–
Mode Register Definition
Standard mode register
Status register
Extended mode register
Reserved
0
BA0
M6
0
0
0
0
1
1
1
1
Operating Mode
Normal operation
All other states reserved
n
An ...
Operating Mode
M5
172
...
0
0
1
1
0
0
1
1
10
A10
M4
0
1
0
1
0
1
0
1
9
A9
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
8
A8
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2
3
7
A7 A6 A5 A4 A3
CAS Latency BT
6
5
4
M3
0
1
3
Burst Length
Standard Mode Register
t
MRD before initiating the subse-
M2
2
0
0
0
0
1
1
1
1
A2 A1 A0
Burst Type
Interleaved
Sequential
M1
1
0
0
1
1
0
0
1
1
0
M0
© 2009 Micron Technology, Inc. All rights reserved.
0
1
0
1
0
1
0
1
Standard mode register (Mx)
Reserved
Reserved
Reserved
Reserved
M3 = 0
Address bus
16
Burst Length
2
4
8
Reserved
Reserved
Reserved
Reserved
M3 = 1
16
2
4
8