MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 56

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

Table 19: Feature Addresses 80h: Programmable I/O Drive Strength
Table 20: Feature Addresses 81h: Programmable R/B# Pull-Down Strength
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Subfeature
Parameter
P1
I/O drive strength
P2
P3
P4
Subfeature
Parameter
P1
R/B# pull-down
strength
P2
P3
P4
Options
Full (default)
Three-quarters
One-half
One-quarter
Options
Full (default)
Three-quarters
One-half
One-quarter
Note:
Note:
1. The programmable drive strength feature address is used to change the default I/O
1. This feature address is used to change the default R/B# pull-down strength. Its strength
drive strength. Drive strength should be selected based on expected loading of the mem-
ory bus. This table shows the four supported output drive strength settings. The default
drive strength is full strength. The device returns to the default drive strength mode
when the device is power cycled. AC timing parameters may need to be relaxed if I/O
drive strength is not set to full.
should be selected based on the expected loading of R/B#. Full strength is the default,
power-on value.
I/O7
I/O7
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
I/O6
I/O6
Reserved (0)
Reserved (0)
Reserved (0)
I/O5
I/O5
Reserved (0)
Reserved (0)
Reserved (0)
Reserved (0)
56
I/O4
I/O4
Reserved (0)
Reserved (0)
Reserved (0)
Micron Technology, Inc. reserves the right to change products or specifications without notice.
I/O3
I/O3
I/O2
I/O2
I/O1
I/O1
0
0
1
1
0
0
1
1
Feature Operations
© 2009 Micron Technology, Inc. All rights reserved.
I/O0
I/O0
0
1
0
1
0
1
0
1
Value
Value
00h
01h
02h
03h
00h
00h
00h
00h
01h
02h
03h
00h
00h
00h
Notes
Notes
1
1