EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 101

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 4: DSP Blocks in Arria II Devices
Arria II Operational Mode Descriptions
Figure 4–20. Rounding and Saturation Locations
December 2010 Altera Corporation
1
16 User defined SAT Positions (bit 43-28)
43
43
Two saturation modes are supported in Arria II devices:
■
■
You must select one of the two options at compile time.
In 2’s complement format, the maximum negative number that can be represented is
–2
the maximum negative number to –2
■
■
Table 4–8
36-bits.
Table 4–8. Examples of Saturation
Arria II devices have up to 16 configurable bit positions out of the 44-bit bus ([43:0])
for the rounding and saturate logic unit, providing higher flexibility. You must select
the 16 configurable bit positions at compile time. These 16-bit positions are located at
bits [21:6] for rounding and [43:28] for saturation, as shown in
For symmetric saturation, the RND bit position is to determine where the LSP for the
saturated data is located.
You can use the rounding and saturation function as described in regular supported
multiplication operations shown in
type operations, the following convention is used.
The functionality of the rounding logic unit is in the format of:
Result = RND[
Likewise, the functionality of the saturation logic unit is in the format of:
Result = SAT[
(n-1)
42
42
Asymmetric saturation mode
Symmetric saturation mode
Asymmetric 32-bit saturation: Max = 0 × 7FFFFFFF, Min = 0 × 80000000
Symmetric 32-bit saturation: Max = 0 × 7FFFFFFF, Min = 0 × 80000001
44 to 36 Bits Saturation
, and the maximum positive number is 2
5926AC01342h
ADA38D2210h
lists how the saturation works. In this example, a 44-bit input is saturated to
∑
∑
(A × B)], when used for an accumulation type of operation.
(A × B)], when used for an accumulation type of operation.
29
28
16 User defined RND Positions (bit 21-6)
21
20
Symmetric SAT Result
Table 4–2 on page
Arria II Device Handbook Volume 1: Device Interfaces and Integration
800000001h
(n-1)
7FFFFFFFFh
+ 1. For example, for 32 bits:
(n-1)
7
– 1. Symmetrical saturation limits
6
4–7. However, for accumulation
Asymmetric SAT Result
1
0
0
800000000h
Figure
7FFFFFFFFh
4–20.
4–29