EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 413

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Receiver Channel Datapath
December 2010 Altera Corporation
The CDR operates in two modes:
■
■
The CDR must be kept in LTR mode until it locks to the input reference clock after the
power-up and reset cycle. When locked to the input reference clock, the CDR output
clock is trained to the configured data rate and can switch to LTD mode to recover the
clock from the incoming data. You can use the optional input ports
(rx_locktorefclk and rx_locktodata) to control the LTR or LTD mode manually or
let the lock happen automatically.
Table 1–8
controller lock mode.
Table 1–8. Optional Input Ports and LTR/LTD Controller Lock Mode for Arria II Devices
Note to
(1) If you do not instantiate the optional rx_locktorefclk and rx_locktodata signals in the ALTGX megafunction,
LTR mode—The PFD in the CDR tracks the receiver input reference clock
(rx_cruclk) and controls the charge pump that tunes the VCO in the CDR. An
active high rx_pll_locked status signal is asserted to indicate that the CDR has
locked to phase and frequency of the receiver input reference clock. In this mode,
the phase detector is inactive.
1
LTD mode—The phase detector in the CDR tracks the incoming serial data at the
receiver input buffer to keep the recovered clock phase-matched to the data.
Depending on the phase difference between the incoming data and the CDR
output clock, the phase detector controls the CDR charge pump that tunes the
VCO.
f
In this mode, the PFD and the /M divider block are inactive. In addition, the
rx_pll_locked signal toggles randomly and has no significance in LTD mode.
The CDR must be in LTD mode to recover the clock from the incoming serial data
during normal operation. The actual LTD lock time depends on the transition
density of the incoming data and the PPM difference between the receiver input
reference clock and the upstream transmitter reference clock. The receiver PCS
logic must be held in reset until the CDR asserts the rx_freqlocked signal and
produces a stable recovered clock.
rx_locktorefclk
the Quartus II software automatically configures the LTR/LTD controller in automatic lock mode.
Table
lists the relationship between the optional input ports and the LTR/LTD
X
Depending on the data rate and the selected input reference clock
frequency, the Quartus II software automatically selects the appropriate
divider values such that the CDR output clock frequency is half the data
rate. This includes the pre-divider before the PFD.
For more information about receiver reset recommendations, refer to the
Reset Control and Power Down
1
0
1–8:
rx_locktodata
0
1
0
chapter.
Arria II Device Handbook Volume 2: Transceivers
LTR/LTD Controller Lock Mode
Automatic Lock Mode
Manual – LTR Mode
Manual – LTD Mode
(Note 1)
1–27