EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 288
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
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- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
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9–8
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Configuration Error
Initialization
1
A reconfiguration is initiated by toggling the nCONFIG pin from high to low and then
back to high with a minimum t
configuration error, initialization, or user mode stage. When nCONFIG is pulled low,
nSTATUS and CONF_DONE are also pulled low and all the I/O pins are tri-stated. After
nCONFIG and nSTATUS return to a logic-high level, configuration begins.
If an error occurs during configuration, Arria II devices assert the nSTATUS signal low,
indicating a data frame error; the CONF_DONE signal stays low. If you turn on the
Auto-restart configuration after error option (available in the Quartus II software
from the General tab of the Device and Pin Options dialog box), the Arria II device
resets the configuration device and retries the configuration. If you turn off this
option, the system must monitor nSTATUS for errors and then pulse nCONFIG low to
restart the configuration.
In Arria II devices, the initialization clock source is either the internal oscillator or the
optional CLKUSR pin. By default, the internal oscillator is the clock source for
initialization. If you use the internal oscillator, the Arria II device provides itself with
enough clock cycles for proper initialization. Therefore, if the internal oscillator is the
initialization clock source, sending the entire configuration file to the device is
sufficient to configure and initialize the device. Driving DCLK to the device after
configuration is complete does not affect device operation.
You also have the flexibility to synchronize initialization of multiple devices or to
delay initialization with the CLKUSR option. You can turn on the Enable
user-supplied start-up clock (CLKUSR) option in the Quartus II software from the
General tab of the Device and Pin Options dialog box. If you supply a clock on
CLKUSR, it does not affect the configuration process. After all the configuration data is
accepted and CONF_DONE goes high, CLKUSR is enabled after the time specified as
t
clock cycles to initialize properly and enter user mode as specified in the t
parameter.
Two DCLK falling edges are required after CONF_DONE goes high to begin the
initialization of the device for both uncompressed and compressed bitstream in the
FPP or PS configuration mode.
CD2CU
. After this time period elapses, Arria II devices require a minimum number of
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
CFG
low-pulse width either in the configuration,
December 2010 Altera Corporation
Configuration Process
CD2UM C
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