EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 212
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Manufacturer
Quantity
Price
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7–16
Figure 7–13. Number of DQ/DQS Groups per Bank in EP2AGZ300 and EP2AGZ350 Devices in the 1152-Pin FineLine BGA
Package
Notes to
(1) These numbers are preliminary until the devices are available.
(2) You can also use DQS/DQSn pins in some of the ×4 groups as R
(3) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
(4) You can also use some of the DQ/DQS pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQ/DQS group with any of its pin members
(5) These ×32/×36 DQ/DQS groups have 40 pins instead of 48 pins per group.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
of the ×4 group are used as R
can use the ×16/×18 or ×32/×36 groups that include that ×4 group; however, there are restrictions on using ×8/×9 groups that include that ×4
group.
used for configuration purposes. Ensure that the DQ/DQS groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQ/DQS groups, depending on your configuration scheme.
Figure
(Note
48 User I/Os
I/O Bank 1A
42 User I/Os
I/O Bank 1C
×16/×18=1
×16/×18=1
7–13:
×8/×9=3
×8/×9=3
DLL0
DLL1
×4=7
×4=6
1), (2), (3),
Figure 7–13
EP2AGZ300 and EP2AGZ350 devices in the 1152-pin FineLine BGA package.
×32/×36=1 (5)
×32/×36=1 (5)
40 User I/Os
40 User I/Os
I/O Bank 3A
I/O Bank 8A
×16/×18=1
×16/×18=1
×8/×9=3
×8/×9=3
UP
×4=6
×4=6
(4)
and R
DN
shows the number of DQ/DQS groups per bank in Arria II GZ
pins for OCT calibration. If two pins of a ×4 group are used as R
24 User I/Os
I/O Bank 3B
24 User I/Os
I/O Bank 8B
×16/×18=1
×16/×18=1
×8/×9=2
×8/×9=2
×4=4
×4=4
EP2AGZ300 and EP2AGZ350 Devices
I/O Bank 8C
32 User I/Os 32 User I/Os
32 User I/Os
in the 1152-Pin FineLine BGA
I/O Bank 3C
×16/×18=0
×16/×18=0
×8/×9=1
×8/×9=1
×4=3
×4=3
UP
and R
32 User I/Os 24 User I/Os
I/O Bank 7C
I/O Bank 4C
×16/×18=0
×16/×18=0
DN
×8/×9=1
×8/×9=1
×4=3
pins, but you cannot use a ×4 group for memory interfaces if two pins
×4=3
Chapter 7: External Memory Interfaces in Arria II Devices
24 User I/Os
I/O Bank 4B
I/O Bank 7B
×16/×18=1
×16/×18=1
×8/×9=2
×8/×9=2
×4=4
×4=4
Memory Interfaces Pin Support for Arria II Devices
×32/×36=1 (5)
×32/×36=1 (5)
40 User I/Os
40 User I/Os
×16/×18=1
I/O Bank 4A
I/O Bank 7A
×16/×18=1
×8/×9=3
×8/×9=3
×4=6
UP
×4=6
and R
December 2010 Altera Corporation
DN
pins for OCT calibration, you
48 User I/Os
I/O Bank 6A
42 User I/Os
I/O Bank 6C
×16/×18=1
×16/×18=1
×8/×9=3
×8/×9=3
DLL3
DLL2
×4=7
×4=6
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