EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 234
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
- EP2AGX45CU17C6N PDF datasheet #3
- EP2AGX45CU17C6N PDF datasheet #4
- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
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7–38
Figure 7–25. IOE Input Registers for Arria II GX Devices
Notes to
(1) You can bypass each register block in this path.
(2) The input clock can be from the DQS logic block (whether the postamble circuitry is bypassed or not) or from a global clock line.
(3) This input clock comes from the CQn logic block.
(4) The DQS signal must be inverted for DDR interfaces except for the QDR II+/QDR II SRAM interfaces. This inversion is done automatically if you
Arria II Device Handbook Volume 1: Device Interfaces and Integration
use the Altera external memory interface IPs.
Figure
DQS (2), (4)
DQSn
CQn (3)
7–25:
DQ
Differential
Buffer
Input
datain
Figure 7–25
consists of DDR input registers and resynchronization registers. You can bypass each
block of the input path.
1
0
Double Data Rate Input Registers
Input Reg B
Input Reg A
D
D
DFF
DFF
Resynchronization
Clock
(resync_clk_2x)
(3)
Q
Q
shows the registers available in the Arria II GX input path. The input path
neg_reg_out
I
I
regouthi
Input Reg C
D
DFF
Q
I
regoutlo
(Note 1)
Synchronization Registers
D
D
DFF
DFF
Chapter 7: External Memory Interfaces in Arria II Devices
Q
Q
Arria II External Memory Interface Features
December 2010 Altera Corporation
To Core (rdata0)
To Core (rdata1)
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