EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 38
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
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- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
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2–10
Figure 2–9. Template for Supported 7-Input Functions in Extended LUT Mode
Note to
(1) If the 7-input function is unregistered, the unused eighth input is available for register packing. The second register, reg1, is not available.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Figure
2–9:
datae0
datae1
dataf0
dataf1
datac
dataa
datab
datad
(1)
Extended LUT Mode
Use extended LUT mode to implement a specific set of 7-input functions. The set must
be a 2-to-1 multiplexer fed by two arbitrary 5-input functions sharing four inputs.
Figure 2–9
mode. In this mode, if the 7-input function is unregistered, the unused eighth input is
available for register packing.
Functions that fit into the template, as shown in
“if-else” statements in Verilog HDL or VHDL code.
This input is available
for register packing.
shows the template of supported 7-input functions using extended LUT
5-Input
5-Input
LUT
LUT
combout0
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices
D
reg0
Figure
Q
2–9, often appear in designs as
December 2010 Altera Corporation
To general or
To general or
local routing
local routing
Adaptive Logic Modules
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