EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 96
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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4–24
Figure 4–17. High-Precision Multiplier Adder Configuration for Half-DSP Block
Note to
(1) Block output for accumulator overflow and saturate overflow.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Figure
High-Precision Multiplier Adder Mode
4–17:
dataA[0:17]
dataB[0:17]
dataA[0:17]
dataB[18:35]
dataC[0:17]
dataD[0:17]
dataC[0:17]
dataD[18:35]
In the high-precision multiplier adder, the DSP block can implement 2 two-multiplier
adders, with a multiplier precision of 18 × 36 (one two-multiplier adder per half-DSP
block). This mode is useful in filtering or FFT applications where a datapath greater
than 18 bits is required, yet 18 bits is sufficient for coefficient precision. This can occur
if data has a high dynamic range. If the coefficients are fixed, as in FFT and most filter
applications, the precision of 18 bits provides a dynamic range over 100 dB, if the
largest coefficient is normalized to the maximum 18-bit representation.
In these situations, the datapath can be up to 36 bits, allowing sufficient capacity for
bit growth or gain changes in the signal source without loss of precision, which is
useful in single precision block floating point applications.
high-precision multiplier is performed in two stages. The sum of the results of the two
adders produce the final result:
Z[54..0] = P
where P
0
= A[17..0] × B[35..0] and P
Half-DSP Block
clock[3..0]
0
ena[3..0]
aclr[3..0]
[53..0] + P
1
<<18
<<18
[53..0]
+
+
P
P
0
1
signa
signb
1
= C[17..0] × D[35..0]
+
Chapter 4: DSP Blocks in Arria II Devices
overflow (1)
Arria II Operational Mode Descriptions
Figure 4–17
December 2010 Altera Corporation
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