EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 541
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
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- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
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Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric-Transceiver Interface Clocking
December 2010 Altera Corporation
Because the recovered clock rx_clkout signals from all 16 channels have a 0 PPM
frequency difference, you can use a single rx_clkout to clock the receiver phase
compensation FIFO in all 16 channels, resulting in only one global or regional clock
resource being used instead of 16. To implement this clocking scheme, you must select
the receiver phase compensation FIFO read clocks instead of the Quartus II software
automatic selection, as described in the
FIFO Read Clock”
User-Selected Receiver Phase Compensation FIFO Read Clock
The ALTGX MegaWizard Plug-In Manager provides an optional rx_coreclk port for
each instantiated receiver channel. If you enable this port, the Quartus II software
does not automatically select the receiver phase compensation FIFO read clock source.
Instead, the signal that you drive on the rx_coreclk port of the channel clocks the
read side of its receiver phase compensation FIFO.
You can use the flexibility of selecting the receiver phase compensation FIFO read
clock to reduce clock resource utilization (global, regional, or both). You can connect
the rx_coreclk ports of all the receiver channels in your design and drive them using
a common clock driver that has a 0 PPM frequency difference with respect to the FIFO
write clocks of these channels. Use this common clock driver to latch the receiver data
and status signals in the FPGA fabric for these channels. This FPGA fabric transceiver
interface clocking scheme uses only one global or regional clock resource for all
channels.
section.
“User-Selected Receiver Phase Compensation
Arria II Device Handbook Volume 2: Transceivers
2–51
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