EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 441
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
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Chapter 1: Transceiver Architecture in Arria II Devices
Functional Modes
Figure 1–54. Transceiver Configurations in Basic Double-Width Mode with a 20-Bit PMA-PCS Interface for Arria II
Devices
Notes to
(1) The maximum data rate specification shown in
(2) The byte ordering block is available only if you select the word alignment pattern length of 20 bits.
(3) Arria II GX I3 devices can support up to 6.375 Gbps. For more information, refer to the
December 2010 Altera Corporation
FPGA Fabric-to-Transceiver
Interface Width
Functional Mode
Data Rate (Gbps) (2)
Number of Channels
Low-Latency PCS
Word Aligner (Pattern Length)
8B/10B Encoder/Decoder
Rate Match FIFO
Byte SERDES
Data Rate (Gbps)
Byte Ordering
FPGA Fabric-to-Transceiver
Interface Frequency (MHz)
TX PCS Latency (FPGA
Fabric-Transceiver Interface
Clock Cycles)
RX PCS Latency (FPGA
Fabric-Transceiver Interface
Clock Cycles)
Figure
1–54:
Figure 1–54
functional mode with a 20-bit PMA-PCS interface.
Disabled
Disabled
1.0 - 5.0
10 - 12
20-Bit
5 - 6
50 -
250
Disabled
Disabled
Disabled
Manual Alignment
4 - 5.5
40-Bit
212.5
6.5 -
25 -
(7-, 10-, 20-Bit)
8.5
1.0 - 6.375
Enabled
Enabled(2)
shows Arria II transceiver configurations allowed in Basic double-width
40-Bit
4 - 5.5
212.5
25 -
6.5 -
8.5
Figure 1–54
1.0 - 5.0
Disabled
Disabled
16-Bit
10 - 12
50 -
250
5 - 6
Disabled
Disabled
32-Bit
4 - 5.5
212.5
25 -
6.5 -
1.0 - 6.375
8.5
is valid only for the -3 (fastest) speed grade devices.
Enabled
Enabled(2)
4 - 5.5
Enabled
32-Bit
212.5
25 -
6.5 -
8.5
Disabled
Basic Double-Width 20-Bit PMA-PCS Interface
1.0 - 5.0 1.0 - 6.375
Disabled Enabled
Disabled
16-Bit
22 - 26 13 - 16
5 - 6
50 -
250
Enabled
Disabled
32-Bit
212.5
4 - 5.5
25 -
1.0 - 6.375 (3)
×1, ×4, ×8
Device Datasheet for Arria II
1.0 - 5.0 1.0 - 6.375 1.0 - 5.0 1.0 - 6.375
Disabled Enabled
Disabled
10 - 12
20-Bit
50 -
250
5 - 6
Disabled
Disabled
Arria II Device Handbook Volume 2: Transceivers
Disabled
40-Bit
4 - 5.5
212.5
6.5 -
25 -
(7-, 10-, 20-Bit)
8.5
Bit Slip
Disabled Enabled
Disabled
10 - 12
16-Bit
5 - 6
50 -
250
Disabled
Enabled
Disabled
4 - 5.5
32-Bit
212.5
6.5 -
25 -
8.5
Devices.
Disabled
1.0 - 5.0 1.0 - 6.375
Disabled
10-Bit
3 - 4
4 - 5
50 -
250
Disabled
Disabled
Disabled
Enabled
Disabled
Enabled
4 - 5.5
3 - 4.5
20-Bit
212.5
25 -
1–55
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