EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 673
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
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- EP2AGX45CU17C6N PDF datasheet #4
- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
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Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–54. High-Speed I/O Specifications for Arria II GZ Devices
December 2010 Altera Corporation
Clock
f
frequency) true
differential I/O
standards
f
frequency) single
ended I/O standards
f
frequency) single
ended I/O standards
f
clock frequency)
Transmitter
f
output data rate)
f
LVDS_E_3R output
data rate)
LVDS_E_1R output
data rate)
t
t
differential I/O
standards with three
external output resistor
network
f
HSCLK_in
HSCLK_in
(9)
HSCLK_in
(10)
HSCLK_OUT
HSDR
HSDR
x Jitter
x Jitter
HSDR
(emulated
(true LVDS
-
(emulated
Symbol
emulated
(input clock
(input clock
(input clock
(output
(5)
Table 1–54
(using DDR registers)
SERDES factor J = 2,
SERDES factor J = 1,
SERDES factor, J = 3
SERDES factor J = 4
Clock boost factor
Clock boost factor
Clock boost factor
Total jitter for data
Total jitter for data
Total jitter for data
Total jitter for data
rate, 600 Mbps to
rate, 600 Mbps to
rate, < 600 Mbps
(using dedicated
rate < 600 Mbps
W = 1 to 40
W = 1 to 40
W = 1 to 40
(uses an SDR
SERDES)
Conditions
1.25 Gbps
1.6 Gbps
register)
to 10
to 10
—
lists the high-speed I/O timing for Arria II GZ devices.
(8)
(3)
(3)
(3)
Min
—
—
—
—
(4)
(4)
(4)
(4)
(4)
5
5
5
5
C3, I3
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
(Note 1), (2), (10)
717
1250
1152
Max
717
717
420
200
160
300
0.1
0.2
(4)
(4)
(7)
Min
—
—
—
—
(4)
(4)
(4)
(4)
(4)
5
5
5
5
(Part 1 of 3)
C4, I4
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
717
1250
Max
0.25
717
717
420
800
200
160
325
0.1
(4)
(4)
(7)
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
Unit
ps
UI
ps
UI
1–69
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