EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 314
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
- EP2AGX45CU17C6N PDF datasheet #3
- EP2AGX45CU17C6N PDF datasheet #4
- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
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- Download datasheet (22Mb)
9–34
Table 9–13. JTAG Pins Signals (Part 2 of 2)
Figure 9–16. JTAG Configuration of a Single Device Using a Download Cable
Notes to
(1) Connect the pull-up resistors to the V
(2) Connect the pull-up resistor to the same supply voltage, V
(3) Resistor value can vary from 1 K
(4) You must connect nCE to GND or drive it low for successful JTAG configuration.
(5) Connect the nCONFIG and MSEL pins to support a non-JTAG configuration scheme. If you only use the JTAG configuration, connect nCONFIG to
(6) In the USB-Blaster, ByteBlaster II, and ByteBlasterMV cables, this pin is a no connect.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
TMS
TCK
TRST
Note to
(1) The TRST pin is only available for Arria II GZ devices.
(1)
Name
Pin
devices.
ByteBlaster II, ByteBlasterMV, EthernetBlaster, EthernetBlaster II, or MasterBlaster cable.
V
CCIO
Figure
Table
for Arria II GX device, V
Test mode
select
Test clock
input
Test reset
input
(optional)
9–13:
Pin Type
9–16:
During JTAG configuration, you can download data to the device on the PCB through
the USB-Blaster, MasterBlaster, ByteBlaster II, ByteBlasterMV, EthernetBlaster, or
EthernetBlaster II download cable.
Figure 9–16
Input pin that provides the control signal to determine the transitions of the TAP controller state
machine. TMS is evaluated on the rising edge of TCK. Therefore, you must set up TMS before the
rising edge of TCK. Transitions within the state machine occur on the falling edge of TCK after the
signal is applied to TMS. If the JTAG interface is not required on your board, you can disable the
JTAG circuitry by connecting this pin to logic high.
Clock input to the BST circuitry. Some operations occur at the rising edge, while others occur at
the falling edge. If the JTAG interface is not required on your board, you can disable the JTAG
circuitry by connecting TCK to GND.
Active-low input to asynchronously reset the boundary-scan circuit. The TRST pin is optional
according to the IEEE Std. 1149.1 standard. If the JTAG interface is not required on your board,
you can disable the JTAG circuitry by connecting the TRST pin to GND. One kΩ pull-up resistor to
V
CCPD
CCPGM
V
CCIO
Ω
if you do not use the TRST pin.
(1)
/V
for Arria II GZ device, and MSEL to GND. Pull DCLK either high or low, whichever is convenient on your board.
to 10 K
CCPGM
V
10
CCIO
CCIO
kΩ
shows the JTAG configuration of a single Arria II device.
(1)
/V
power supply of I/O bank 3C for Arria II GX devices and to V
GND
CCPGM
Ω
10
(5)
(5)
(5)
.
kΩ
N.C.
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
nCE
nCE0
nSTATUS
CONF_DONE
nCONFIG
MSEL[n..0]
DCLK
Arria II Device
(4)
CCIO
for Arria II GX devices or V
TDO
TMS
TCK
TDI
V
(3)
CCIO
(2)
/V
V
CCPD
CCIO
Description
(2)
/V
(3)
CCPD
1
kΩ
GND
Pin 1
CCPD
10-Pin Male Header
Download Cable
(JTAG Mode)
for Arria II GZ devices as the USB-Blaster,
(Top View)
GND
V
CCPGM
CCIO
V
IO
(2)
(6)
/V
GND
CCPD
at a 3.0-V power supply for Arria II GZ
December 2010 Altera Corporation
JTAG Configuration
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