EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 89
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
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- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
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Chapter 4: DSP Blocks in Arria II Devices
Arria II Operational Mode Descriptions
Figure 4–10. 36-Bit Independent Multiplier Mode Shown for Half-DSP Block
December 2010 Altera Corporation
dataa_0[35..18]
datab_0[35..18]
datab_0[35..18]
dataa_0[35..18]
dataa_0[17..0]
datab_0[17..0]
dataa_0[17..0]
datab_0[17..0]
clock[3..0]
ena[3..0]
aclr[3..0]
36-Bit Multiplier
You can construct a 36 × 36 multiplier with four 18 × 18 multipliers. This
simplification fits into one half-DSP block and is implemented in the DSP block
automatically by selecting 36 × 36 mode. Arria II devices can have up to two 36-bit
multipliers per DSP block (one 36-bit multiplier per half DSP block). The 36-bit
multiplier is also under the independent multiplier mode but uses the entire half-DSP
block, including the dedicated hardware logic after the pipeline registers to
implement the 36 × 36-bit multiplication operation, as shown in
The 36-bit multiplier is useful for applications requiring more than 18-bit precision;
for example, for the mantissa multiplication portion of single precision and extended
single precision floating-point arithmetic applications.
Half-DSP Block
signa
signb
+
+
Arria II Device Handbook Volume 1: Device Interfaces and Integration
+
72
Figure
result[ ]
4–10.
4–17
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