EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 134
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
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- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
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5–30
Figure 5–24. ZDB Mode in PLLs for Arria II GZ Devices
Arria II Device Handbook Volume 1: Device Interfaces and Integration
1
1
inclk
Zero-Delay Buffer Mode
In ZDB mode, the external clock output pin is phase-aligned with the clock input pin
for zero delay through the device. You must use the same I/O standard on the input
and output clocks to guarantee clock alignment at the input and output pins. Zero-
delay buffer mode is supported on all Arria II PLLs.
You must instantiate a bidirectional I/O pin in the design to serve as the feedback
path connecting the FBOUT and FBIN ports of the PLL when using Arria II GZ PLLs in
ZDB mode, along with single-ended I/O standards, to ensure phase alignment
between the CLK pin and the external clock output (CLKOUT) pin. The PLL uses this
bidirectional I/O pin to mimic and compensate for the output delay from the clock
output port of the PLL to the external clock output pin.
The bidirectional I/O pin that you instantiate in your design must always be assigned
a single-ended I/O standard.
Do not place board traces on the bidirectional I/O pin when using ZDB mode, to
avoid signal reflection.
Figure 5–24
standards on the PLL clock input or output pins.
÷n
shows ZDB mode in Arria II GZ PLLs. You cannot use differential I/O
PFD
CP/LF
VCO
÷C0
÷C1
÷m
Chapter 5: Clock Networks and PLLs in Arria II Devices
fbout
fbin
PLL_<#>_CLKOUT#
PLL_<#>_CLKOUT#
December 2010 Altera Corporation
bidirectional
I/O pin
PLLs in Arria II Devices
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