ISP1161A1BM ST-Ericsson Inc, ISP1161A1BM Datasheet - Page 94

• Manufacturer Part Number: ISP1161A1BM
• Description: IC USB HOST/DEVICE CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161A1BM

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1163; ISP1161A1BM,557

Philips Semiconductors
Table 76:
Table 78:
9397 750 13961
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
DcEndpointConfiguration register: bit allocation
DcAddress register: bit allocation
FIFOEN
DEVEN
R/W
R/W
7
0
7
0
13.1.2 DcAddress register (R/W: B7H/B6H)
Transaction — write/read 1 word
Table 77:
This command is used to set the USB assigned address in the DcAddress register
and enable the USB device. The DcAddress register bit allocation is shown in
Table
A USB bus reset sets the device address to 00H (internally) and enables the device.
The value of the DcAddress register (accessible by the microcontroller) is not altered
by the bus reset. In response to the standard USB request, Set Address, the firmware
must issue a Write Device Address command, followed by sending an empty packet
to the host. The new device address is activated when the host acknowledges the
empty packet.
Code (Hex): B6/B7 — write/read DcAddress register
Transaction — write/read 1 word
Table 79:
Bit
7
6
5
4
3 to 0
Bit
7
6 to 0
EPDIR
R/W
R/W
6
0
6
0
78.
DcEndpointConfiguration register: bit description
DcAddress register: bit description
Symbol
FIFOEN
EPDIR
DBLBUF
FFOISO
FFOSZ[3:0]
Symbol
DEVEN
DEVADR[6:0]
DBLBUF
R/W
R/W
5
0
5
0
Rev. 03 — 23 December 2004
FFOISO
Description
A logic 1 indicates an enabled FIFO with allocated memory.
A logic 0 indicates a disabled FIFO (no bytes allocated).
This bit defines the endpoint direction (0 = OUT, 1 = IN); it also
determines the DMA transfer direction (0 = read, 1 = write).
A logic 1 indicates that this endpoint has double buffering.
A logic 1 indicates an isochronous endpoint. A logic 0 indicates
a bulk or interrupt endpoint.
Selects the FIFO size according to
Description
A logic 1 enables the device.
This field specifies the USB device address.
R/W
R/W
4
0
4
0
DEVADR[6:0]
USB single-chip host and device controller
R/W
R/W
3
0
3
0
R/W
R/W
2
0
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
FFOSZ[3:0]
Table 67
ISP1161A1
R/W
R/W
1
0
1
0
R/W
R/W
93 of 136
0
0
0
0