ISP1161A1BM ST-Ericsson Inc, ISP1161A1BM Datasheet - Page 97

• Manufacturer Part Number: ISP1161A1BM
• Description: IC USB HOST/DEVICE CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161A1BM

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1163; ISP1161A1BM,557

Philips Semiconductors
9397 750 13961
Product data
13.1.5 DcInterruptEnable register (R/W: C3H/C2H)
Table 83:
This command is used to individually enable or disable interrupts from all endpoints,
as well as interrupts caused by events on the USB bus (SOF, SOF lost, EOT,
suspend, resume, reset). That is, if an interrupt event occurs while the interrupt is not
enabled, nothing will be seen on the interrupt pin. Even if you then enable the
interrupt during the interrupt event, there will still be no interrupt seen on the interrupt
pin, see
The DcInterrupt register will not register any interrupt, if it is not already enabled
using the DcInterruptEnable register. The DcInterruptEnable register is not an
Interrupt Mask register.
A bus reset will not change any of the programmed bit values.
The command accesses the DcInterruptEnable register, which consists of 4 bytes.
The bit allocation is given in
Remark: For details on interrupt control, see
Bit
3
2
1
0
Fig 42. Interrupt pin waveform.
Pin INT2: HIGH = de-assert; LOW = assert; INTENA = 1.
Figure
DcHardwareConfiguration register: bit description
Symbol
WKUPCS
PWROFF
INTLVL
INTPOL
42.
Rev. 03 — 23 December 2004
INT2 pin
DcInterruptEnable
disabled
register
interrupt
occurs
event
Description
A logic 1 enables remote wake-up via a LOW level on input
pin CS (V
Bus reset value: unchanged.
A logic 1 enables powering-off during ‘suspend’ state. Output
D_SUSPEND pin is configured as a power switch control signal
for external devices (HIGH during ‘suspend’). This value should
always be initialized to logic 1. Bus reset value: unchanged.
Selects the interrupt signalling mode on output pin INT2
(0 = level, 1 = pulsed). In pulsed mode an interrupt produces an
166 ns pulse. See
Bus reset value: unchanged.
Selects INT2 pin signal polarity (0 = active LOW, 1 = active
HIGH). Bus reset value: unchanged.
Table
DcInterruptEnable
84.
BUS
enabled
register
USB single-chip host and device controller
must be present for wake-up on CS).
Section 8.6.3
Section
interrupt
occurs
event
interrupt is cleared
8.6.3.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
for details.
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