FDC37C669-MT SMSC, FDC37C669-MT Datasheet - Page 101

• Manufacturer Part Number: FDC37C669-MT
• Description: IC CTRLR SUPER I/O FLPPY 100TQFP
• Manufacturer: SMSC

Specifications of FDC37C669-MT

• Controller Type: I/O Controller
• Interface: ISA Host
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 25mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1008

Data bytes are always read from the head of tFIFO
regardless of the value of the direction bit. For example if
44h, 33h, 22h is written to the FIFO, then reading the
tFIFO will return 44h, 33h, 22h in the same order as was
written.
cnfgA (Configuration Register A)
ADDRESS OFFSET = 400H
Mode = 111
This register is a read only register. When read, 10H is
returned. This indicates to the system that this is an 8-bit
implementation. (PWord = 1 byte)
cnfgB (Configuration Register B)
ADDRESS OFFSET = 401H
Mode = 111
BIT 7 compress
This bit is read only. During a read it is a low level.
This means that this chip does not support hardware RLE
compression. It does support hardware de-compression!
BIT 6 intrValue
Returns the value on the ISA iRq line to determine
possible conflicts.
BITS 5:0 Reserved
During a read are a low level. These bits cannot be
written.
ecr (Extended Control Register)
ADDRESS OFFSET = 402H
Mode = all
This register controls the extended ECP parallel port
functions.
BITS 7,6,5
These bits are Read/Write and select the Mode.
BIT 4 nErrIntrEn
Read/Write (Valid only in ECP Mode)
1:
0:
Disables the interrupt generated on the asserting
edge of nFault.
Enables an interrupt pulse on the high to low edge of
nFault. Note that an interrupt will be generated if
101
BIT 3 dmaEn
Read/Write
1:
0:
BIT 2 serviceIntr
Read/Write
1:
0:
case dmaEn=1:
case dmaEn=0 direction=0:
case dmaEn=0 direction=1:
BIT 1 full
Read only
1:
0:
BIT 0 empty
Read only
1:
0:
nFault is asserted (interrupting) and this bit is written
from a 1 to a 0. This prevents interrupts from being
lost in the time between the read of the ecr and the
write of the ecr.
Enables DMA (DMA starts when serviceIntr is 0).
Disables DMA unconditionally.
Disables DMA and all of the service interrupts.
Enables one of the following 3 cases of interrupts.
Once one of the 3 service interrupts has occurred
serviceIntr bit shall be set to a 1 by hardware, it must
be reset to 0 to re-enable the interrupts. Writing this
bit to a 1 will not cause an interrupt.
During DMA (this bit is set to a 1 when terminal count
is reached).
This bit shall be set to 1 whenever there are
writeIntrThreshold or more bytes free in the FIFO.
This bit shall be set to 1 whenever there are
readIntrThreshold or more valid bytes to be read
from the FIFO.
The FIFO cannot accept another byte or the FIFO is
completely full.
The FIFO has at least 1 free byte.
The FIFO is completely empty.
The FIFO contains at least 1 byte of data.