FDC37C669-MT SMSC, FDC37C669-MT Datasheet - Page 105

• Manufacturer Part Number: FDC37C669-MT
• Description: IC CTRLR SUPER I/O FLPPY 100TQFP
• Manufacturer: SMSC

Specifications of FDC37C669-MT

• Controller Type: I/O Controller
• Interface: ISA Host
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 25mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1008

are always possible with standard or PS/2 mode using
program control of the control signals.
Interrupts
The interrupts are enabled by serviceIntr in the ecr
register.
serviceIntr = 1
serviceIntr = 0
The interrupt generated is ISA friendly in that it must
pulse the interrupt line low, allowing for interrupt sharing.
After a brief pulse low following the interrupt event, the
interrupt line is tri-stated so that other interrupts may
assert.
An interrupt is generated when:
1. For DMA transfers: When serviceIntr is 0, dmaEn is
2. For Programmed I/O:
1 and the DMA TC is received.
a.
When serviceIntr is 0, dmaEn is 0, direction is
0 and there are writeIntrThreshold or more free
bytes in the FIFO.
generated when serviceIntr is cleared to 0
whenever there are writeIntrThreshold or more
free bytes in the FIFO.
Disables the DMA and all of the
service interrupts.
Enables
condition. If the interrupting condition
is valid, then the interrupt is generated
immediately when this bit is changed
from a 1 to a 0. This can occur during
Programmed I/O if the number of bytes
removed or added from/to the FIFO
does not cross the threshold.
the
Also, an interrupt is
selected
interrupt
105
3. When nErrIntrEn is 0 and nFault transitions from high
4. When ackIntEn is 1 and the nAck signal transitions
FIFO Operation
The FIFO threshold is set in the chip configuration
registers. All data transfers to or from the parallel port
can proceed in DMA or Programmed I/O (non-DMA)
mode as indicated by the selected mode. The FIFO is
used by selecting the Parallel Port FIFO mode or ECP
Parallel Port Mode. (FIFO test mode will be addressed
separately). After a reset, the FIFO is disabled. Each
data byte is transferred by a Programmed I/O cycle or
PDRQ depending on the selection of DMA or
Programmed I/O mode.
The following paragraphs detail the operation of the FIFO
flow control. In these descriptions, <threshold> ranges
from 1 to 16. The parameter FIFOTHR, which the user
programs, is one less and ranges from 0 to 15.
A low threshold value (i.e. 2) results in longer periods of
time between service requests, but requires faster
servicing of the request for both read and write cases.
The host must be very responsive to the service request.
This is the desired case for use with a "fast" system.
b.
to low or when nErrIntrEn is set from 1 to 0 and nFault
is asserted.
from a low to a high.
(1)
When serviceIntr is 0, dmaEn is 0,
direction
readIntrThreshold or more bytes in the
FIFO. Also, an interrupt is generated
when serviceIntr is cleared to 0
whenever there are readIntrThreshold
or more bytes in the FIFO.
is
1
and
there
are