FDC37C669-MT SMSC, FDC37C669-MT Datasheet - Page 133

• Manufacturer Part Number: FDC37C669-MT
• Description: IC CTRLR SUPER I/O FLPPY 100TQFP
• Manufacturer: SMSC

Specifications of FDC37C669-MT

• Controller Type: I/O Controller
• Interface: ISA Host
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 25mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1008

CR24
This register can only be accessed in the Configuration
Mode and after the CSR has been initialized to 25H.
The default value of this register after power up is 00H.
This register is used to select the base address of UART1
(serial port 1).
CR25
This register can only be accessed in the Configuration
Mode and after the CSR has been initialized to 25H. The
default value of this register after power up is 00H. This
register is used to select the base address of UART2
(serial port 2).
CR26
This register can only be accessed in the Configuration
Mode and after the CSR has been initialized
The default value of this
ADR9
ADR9
DB7
DB7
ADR8
ADR8
DB6
DB6
The serial port can be set to 96
The serial port can be set to 96
ADR7
ADR7
DB5
DB5
D3-D0
D7-D4
ADR6
ADR6
0000
0001
0010
0011
DB4
DB4
to
26H.
ADR5
ADR5
DB3
DB3
133
DMA Selected
locations, on 8 byte boundaries from 100H-3F8H.
disable the serial port, set ADR9 and ADR8 to zero.
Upper Address Decode requirements : nCS='0' and
A10='0' are required to access UART1 registers. A[2:0]
are decoded as XXXb.
locations, on 8 byte boundaries from 100H-3F8H.
disable the serial port, set ADR9 and ADR8 to zero.
Upper Address Decode requirements : nCS='0' and
A10='0' are required to access UART2 registers. A[2:0]
are decoded as XXXb.
register after power up is 00H. This register is used to
select the DMA for the FDC (Bits 4:7) and the parallel
port (bits 3:0).
tristate.
DMA_A
DMA_B
DMA_C
None
ADR4
ADR4
DB2
DB2
Any unselected DMA REQ output is in
ADR3
ADR3
DB1
DB1
DB0
DB0
0
0
To
To