FDC37C669-MT SMSC, FDC37C669-MT Datasheet - Page 112

IC CTRLR SUPER I/O FLPPY 100TQFP

FDC37C669-MT

Manufacturer Part Number
FDC37C669-MT
Description
IC CTRLR SUPER I/O FLPPY 100TQFP
Manufacturer
SMSC
Datasheet

Specifications of FDC37C669-MT

Controller Type
I/O Controller
Interface
ISA Host
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
25mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1008

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
FDC37C669-MT
Manufacturer:
Microchip Technology
Quantity:
10 000
UART Power Management
Direct power management is controlled by CR2 bits 3 and
7. Refer to CR2 bits 3 and 7 for more information.
Auto Power Management is enabled by CR7 bits 5 and 6.
management operations:
1.
2.
Note:
Exit Auto Powerdown
The transmitter exits powerdown on a write to the XMIT
buffer. The receiver exits auto powerdown when RXDx
changes state.
When set, these bit allows the following auto power
The transmitter enters auto powerdown when the
transmit buffer and shift register are empty.
The receiver enters powerdown when the following
conditions are all met:
a.
b.
Receive FIFO is empty
The receiver is waiting for a start bit.
While in powerdown the Ring Indicator interrupt
is still valid and transitions when the RI input
changes.
112
Parallel Port
Direct power management is controlled by CR1 bit 2.
Refer to CR1 bit 2 for more information.
Auto Power Management is enabled by CR7 bit 4. When
set, this bit allows the ECP or EPP logical parallel port
blocks to be placed into powerdown when not being used.
The EPP logic is in powerdown under any of the following
conditions:
1.
2.
The ECP logic is in powerdown under any of the following
conditions:
1.
2
Exit Auto Powerdown
The parallel port logic can change powerdown modes
when the ECP mode is changed through the ecr register
or when the parallel port mode is changed through the
configuration registers.
EPP is not enabled in the configuration registers.
EPP is not selected through ecr while in ECP mode.
ECP is not enabled in the configuration registers.
SPP, PS/2 Parallel port or EPP mode is selected
through ecr while in ECP mode.

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