FDC37C669-MT SMSC, FDC37C669-MT Datasheet - Page 132

• Manufacturer Part Number: FDC37C669-MT
• Description: IC CTRLR SUPER I/O FLPPY 100TQFP
• Manufacturer: SMSC

Specifications of FDC37C669-MT

• Controller Type: I/O Controller
• Interface: ISA Host
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 25mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1008

CR21
This register can only be accessed in the Configuration
Mode and after the CSR has been initialized to 21H.
The default value of this register after
of the IDE Interface Control Registers (0-7).
CR22
This register can only be accessed in the Configuration
Mode and after the CSR has been initialized to 22H. The
default value of this register after power up is 3DH.
This register is used to select the base address of
the IDE Interface Alternate Status Register. This can
be
CR23
This register can only be accessed in the Configuration
Mode and after the CSR has been initialized to 23H. The
default value of this register after power up is 00H. This
register is used
parallel port. If EPP is not enabled, the parallel port can
be set to 192 locations, on 4 byte boundaries from 100H-
3FCH. If EPP is enabled, the parallel
3CH.
ADR9
ADR9
ADR9
DB7
DB7
DB7
set
This register is used to select the base address
to
ADR8
ADR8
ADR8
DB6
DB6
DB6
to
48
select
locations,
ADR7
ADR7
ADR7
DB5
DB5
DB5
the base address of the
EPP Enabled
Yes
No
power
on
ADR6
ADR6
ADR6
DB4
DB4
DB4
16 byte
up
A[1:0] = XXb
A[2:0] = XXXb
This
is
Addressing (low bits) Decode
ADR5
ADR5
ADR5
DB3
DB3
DB3
132
can be set to 48 locations, on 16 byte boundaries from
100H-3F0H.
ADR8 to zero.
Upper Address Decode requirements : nCS='0' and
A10='0' are required to access the IDE registers. A[3:0]
are decoded as 0XXXb.
boundaries+6 from 106H-3F6H. To disable this decode,
set ADR9 and ADR8 to zero.
Upper Address Decode requirements : nCS='0' and
A10='0' are required to access the IDE Alternate Status
register. A[3:0] must be 0110b.
port can be set to 96 locations, on 8 byte boundaries from
100H-3F8H.
ADR8 to zero.
Upper Address Decode requirements : nCS='0' and
A10='0' are required to access the Parallel Port when in
Compatible, Bi-directional, or EPP modes (A10 is active
when in ECP mode).
ADR4
ADR4
ADR4
DB2
DB2
DB2
To disable the parallel port, set ADR9 and
To disable this decode, set ADR9 and
ADR3
DB1
DB1
DB1
0
0
ADR2
DB0
DB0
DB0
0
1