FDC37C669-MT SMSC, FDC37C669-MT Datasheet - Page 27

• Manufacturer Part Number: FDC37C669-MT
• Description: IC CTRLR SUPER I/O FLPPY 100TQFP
• Manufacturer: SMSC

Specifications of FDC37C669-MT

• Controller Type: I/O Controller
• Interface: ISA Host
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 25mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1008

DATA RATE SELECT REGISTER (DSR)
Address 3F4 WRITE ONLY
This register is write only. It is used to program the data
rate, amount of write precompensation, power down
status, and software reset. The data rate is programmed
using the Configuration Control Register (CCR) not the
DSR, for PC/AT and PS/2 Model 30 and
BIT 0 and 1 DATA RATE SELECT
These bits control the data rate of the floppy controller.
See Table 13 for the settings corresponding to the
individual data rates.
unaffected by a software reset, and are set to 250 kbps
after a hardware reset.
BIT 2 through 4 PRECOMPENSATION SELECT
These
precompensation that will be applied to the WDATA
output signal.
values for the combination of these bits settings. Track 0
is
precompensation. this starting track number can be
changed by the configure command.
BIT 5 UNDEFINED
Should be written as a logic "0".
BIT 6 LOW POWER
A logic "1" written to this bit will put the floppy controller
into Manual Low Power mode. The
the
RESET
COND.
three
default
Table 12 shows the precompensation
bits
RESET
starting
S/W
7
0
select
The data rate select bits are
POWER
DOWN
track
6
0
the
number
value
5
0
0
of
to
COMP2
PRE-
4
0
write
start
27
COMP1
PRE-
Microchannel applications. Other applications can set the
data rate in the DSR.
controller is the most recent write of either the DSR or
CCR. The DSR is unaffected by a software reset. A
hardware reset will set the DSR to 02H, which
corresponds to the default precompensation setting and
250 kbps.
floppy controller clock and data separator circuits will be
turned off. The controller will come out of manual low
power mode after a software reset or access to the Data
Register or Main Status Register.
BIT 7 SOFTWARE RESET
This active high bit has the same function as the DOR
RESET (DOR bit 2) except that this bit is self clearing.
3
0
PRECOMP
432
111
001
010
011
100
101
110
000
Table 10 - Precompensation Delays
COMP0
PRE-
2
0
PRECOMPENSATION DELAY
DRATE
SEL1
Default (See Table 14)
1
1
0.00 ns-DISABLED
125.00 ns
166.67 ns
208.33 ns
250.00 ns
The data rate of the floppy
41.67 ns
83.34 ns
DRATE
SEL0
0
0