FDC37C669-MT SMSC, FDC37C669-MT Datasheet - Page 68

• Manufacturer Part Number: FDC37C669-MT
• Description: IC CTRLR SUPER I/O FLPPY 100TQFP
• Manufacturer: SMSC

Specifications of FDC37C669-MT

• Controller Type: I/O Controller
• Interface: ISA Host
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 25mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1008

2. The write pre-compensation given to a perpendicular
3. For D0-D3 programmed to "0" for conventional mode
LOCK
In order to protect systems with long DMA latencies
against older application software that can disable the
FIFO the LOCK Command has been added.
command should only be used by the FDC routines, and
application software should refrain from using it. If an
application calls for the FIFO to be disabled then the
CONFIGURE command should be used.
data rate.
mode drive wil be 0ns.
drives any data written will be at the currently
programmed write pre-compensation.
WGATE
0
0
1
1
Table 29 - Effects of WGATE and GAP Bits
GAP
0
1
0
1
Conventional
Perpendicular
(500 Kbps)
Reserved
(Conventional)
Perpendicular
(1 Mbps)
MODE
This
68
GAP2 FORMAT
Note: Bits D0-D3 can only be overwritten when OW is
Software and hardware resets have the following effect
on the PERPENDICULAR MODE COMMAND:
1. "Software" resets (via the DOR or DSR registers) will
2. "Hardware" resets will clear all bits (GAP, WGATE
The LOCK command defines whether the EFIFO,
FIFOTHR, and PRETRK parameters of the CONFIGURE
command can be RESET by the DOR and DSR
registers.
subsequent "software RESETS by the DOR and DSR
registers will not change the previously set parameters to
their default values.
RESET pin will set the LOCK bit to logic "0" and return
the
LENGTH OF
22 Bytes
22 Bytes
22 Bytes
41 Bytes
FIELD
only clear GAP and WGATE bits to "0". D0-D3 are
unaffected and retain their previous value.
and D0-D3) to "0", i.e all conventional mode.
programmed as a "1".
If either GAP or WGATE is a "1" then D0-D3 are
ignored.
EFIFO,
When the LOCK bit is set to logic "1" all
PORTION OF
WRITTEN BY
WRITE DATA
OPERATION
FIFOTHR,
19 Bytes
38 Bytes
0 Bytes
0 Bytes
GAP 2
All "hardware" RESET from the
and
PRETRK
to