FDC37C669-MT SMSC, FDC37C669-MT Datasheet - Page 9

• Manufacturer Part Number: FDC37C669-MT
• Description: IC CTRLR SUPER I/O FLPPY 100TQFP
• Manufacturer: SMSC

Specifications of FDC37C669-MT

• Controller Type: I/O Controller
• Interface: ISA Host
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 25mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1008

PIN NO.
TQFP
81,91
83,93
82,92
QFP/
nRequest to
Send
(System Option)
nData Terminal
Ready
nClear to Send
NAME
nRTS1
nRTS2
(SYSOPT)
nDTR1
nDTR2
nCTS1
nCTS2
DESCRIPTION OF PIN FUNCTIONS
SYMBOL
BUFFER
TYPE
O4
O4
I
9
Active low Request to Send outputs for the
Serial Port. Handshake output signal notifies
modem that the UART is ready to transmit
data.
writing to bit 1 of Modem Control Register
(MCR).
nRTS signal to inactive mode (high). Forced
inactive during loop mode operation.
At the trailing edge of hardware reset, the
nRTS2 input is latched to determine the
configuration base address.
0 : INDEX Base I/O Address = 3F0 Hex
1 : INDEX Base I/O Address = 370 Hex
Active low Data Terminal Ready outputs for
the serial port.
notifies modem that the UART is ready to
establish data communication link. This signal
can be programmed by writing to bit 0 of
Modem Control Register (MCR).
hardware reset will reset the nDTR signal to
inactive mode (high). Forced inactive during
loop mode operation.
Active low Clear to Send inputs for the serial
port.
UART that the modem is ready to receive
data.
nCTS signal by reading bit 4 of Modem Status
Register (MSR). A nCTS signal state change
from low to high after the last MSR read will
set MSR bit 0 to a 1. If bit 3 of Interrupt
Enable Register is set, the interrupt is
generated when nCTS changes state. The
nCTS signal has no effect on the transmitter.
Note:
nCTS.
Handshake signal which notifies the
The CPU can monitor the status of
This signal can be programmed by
Bit 4 of MSR is the complement of
The hardware reset will reset the
DESCRIPTION
Handshake output signal
The