ICS1893YI-10LF IDT, Integrated Device Technology Inc, ICS1893YI-10LF Datasheet - Page 111
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ICS1893YI-10LF
Manufacturer Part Number
ICS1893YI-10LF
Description
PHYCEIVER LOW PWR 3.3V 64-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
PHYceiver™r
Type
PHY Transceiverr
Specifications of ICS1893YI-10LF
Protocol
MII
Voltage - Supply
3.14 V ~ 3.47 V
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Lead Free Status / Rohs Status
Compliant
Other names
1893YI-10LF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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ICS1893YI-10LF
Manufacturer:
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Company:
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ICS1893YI-10LF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
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ICS1893 Rev C 6/6/00
Table 9-4.
HW/SW
LOCK
LSTA
MII/SI
NOD/REP
REF_IN
REF_OUT
RESETn
Name
ICS1893 - Release
Pin
Configuration Pins (Continued)
Number
Pin
23
27
21
19
53
52
18
1
Output
Output
Type
Input
Input
Input
Input
Input
Input
Pin
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
Hardware/Software (Select).
When the signal on this pin is logic:
(Stream Cipher) Lock (Acquired).
When the signal on this pin is logic:
Link Status.
This pin is used to report the status of the link segment. When the
signal on this pin is logic:
This pin is mapped according to the interface for which the ICS1893 is
mapped. For the:
Media Independent Interface / Stream Interface (Select).
This pin is used in combination with the 10/LP and 10/100SEL pins to
configure the ICS1893 MAC/Repeater Interface. When the signal on
this pin is logic:
Node/Repeater (Select).
This selection on this pin affects both the SQE test and the Carrier
Sense (CSR) signal. When the signal on this pin is logic:
(Frequency) Reference Input.
This pin is connected to a 25-MHz oscillator. For a tolerance, see
Section 10.5.1, “ Timing for Clock Reference In (REF_IN) Pin”
(Frequency) Reference Output.
This pin is eserved and must be left unconnected.
(System) Reset (Active Low).
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low, this pin selects Hardware mode operations.
High, this pin selects Software mode operations.
Low, the ICS1893 does not have a lock on the data stream.
High, the ICS1893 has a lock on the data stream.
Low, there is no link established.
High, there is a link established.
Media Independent Interface (MII), the LSTA is mapped as LSTA.
100M Symbol Interface, the LSTA is mapped as SD.
10M Serial Interface, the LSTA is mapped as LSTA.
Link Pulse Interface, the LSTA is mapped as SD.
Low, this pin configures the MAC/Repeater Interface as a Media
Independent Interface.
High, this pin configures the MAC/Repeater Interface as a Stream
Interface.
Low, this pin enables the ICS1893 to default to node operations.
High, this pin enables the ICS1893 to default to repeater
operations.
When the signal on this active-low pin is logic:
– Low, the ICS1893 is in hardware reset.
– High, the ICS1893 is operational.
For more information on hardware resets, see the following:
–
–
Section 5.1.2.1, “ Hardware Reset”
Section 10.5.18, “ Reset: Hardware Reset and Power-Down”
111
Chapter 9 Pin Diagram, Listings, and Descriptions
Pin Description
June, 2000
.