ICS1893YI-10LF IDT, Integrated Device Technology Inc, ICS1893YI-10LF Datasheet - Page 76
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ICS1893YI-10LF
Manufacturer Part Number
ICS1893YI-10LF
Description
PHYCEIVER LOW PWR 3.3V 64-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
PHYceiver™r
Type
PHY Transceiverr
Specifications of ICS1893YI-10LF
Protocol
MII
Voltage - Supply
3.14 V ~ 3.47 V
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Lead Free Status / Rohs Status
Compliant
Other names
1893YI-10LF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICS1893YI-10LF
Manufacturer:
IDT
Quantity:
390
Company:
Part Number:
ICS1893YI-10LF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
ICS1893YI-10LF
Manufacturer:
IDT
Quantity:
20 000
Company:
Part Number:
ICS1893YI-10LFT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
8.6 Register 4: Auto-Negotiation Register
8.6.1 Next Page (bit 4.15)
ICS1893 Rev C 6/6/00
Table 8-11
capabilities that it wants to advertise to its remote link partner. During the auto-negotiation process, the
ICS1893 advertises (that is, exchanges) capability data with its remote link partner by using a pre-defined
Link Code Word. The Link Code Word is embedded in the Fast Link Pulses exchanged between PHYs
when the ICS1893 has its Auto-Negotiation sublayer enabled. The value of the Link Control Word is
established based on the value of the bits in this register.
Note:
Table 8-11.
† As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value
Note 1:
•
•
This bit indicates whether the ICS1893 uses the Next Page Mode functions during the auto-negotiation
process. If bit 4.15 is logic:
•
•
4.15
4.14
4.13
4.12
4.11
4.10
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4.0
Bit
to all Reserved bits.
In Hardware mode (that is, HW/SW pin is logic zero), this bit is a Read-Only bit.
In Software mode (that is, HW/SW pin is logic one), this bit is a Command Override Write bit.
Zero, then the ICS1893 indicates to its remote link partner that these features are disabled. (Although
the default value of this bit is logic zero, the ICS1893 does support the Next Page function.)
One, then the ICS1893 advertises to its remote link partner that this feature is enabled.
ICS1893 Data Sheet - Release
Next Page
IEEE reserved
Remote fault
IEEE reserved
IEEE reserved
IEEE reserved
100Base-T4
100Base-TX, full duplex
100Base-TX, half duplex Do not advertise ability
10Base-T, full duplex
10Base-T half duplex
Selector Field bit S4
Selector Field bit S3
Selector Field bit S2
Selector Field bit S1
Selector Field bit S0
For an explanation of acronyms used in
lists the bits for the Auto-Negotiation Register. An STA uses this register to select the ICS1893
Definition
Auto-Negotiation Advertisement Register (register 4 [0x04])
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
Next page not supported
Always 0
Locally, no faults detected
Always 0
Always 0
Always 0
Always 0. (Not supported.)
Do not advertise ability
Do not advertise ability
Do not advertise ability
IEEE 802.3-specified default N/A
IEEE 802.3-specified default N/A
IEEE 802.3-specified default N/A
IEEE 802.3-specified default N/A
N/A
When Bit = 0
76
Table
8-5, see
Next page supported
N/A
Local fault detected
N/A
N/A
N/A
N/A
Advertise ability
Advertise ability
Advertise ability
Advertise ability
IEEE 802.3-specified
default
When Bit = 1
Chapter 1, “ Abbreviations and Acronyms”
Chapter 8 Management Register Set
Note 1
Note 1
Note 1
Note 1
cess
R/W
R/W
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
Ac-
SF
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
fault
De-
June, 2000
0†
0†
0†
0†
0
0
0
1
1
1
1
0
0
0
0
1
Hex
E
0
1
1
.