ICS1893YI-10LF IDT, Integrated Device Technology Inc, ICS1893YI-10LF Datasheet - Page 14
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ICS1893YI-10LF
Manufacturer Part Number
ICS1893YI-10LF
Description
PHYCEIVER LOW PWR 3.3V 64-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
PHYceiver™r
Type
PHY Transceiverr
Specifications of ICS1893YI-10LF
Protocol
MII
Voltage - Supply
3.14 V ~ 3.47 V
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Lead Free Status / Rohs Status
Compliant
Other names
1893YI-10LF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICS1893YI-10LF
Manufacturer:
IDT
Quantity:
390
Company:
Part Number:
ICS1893YI-10LF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
ICS1893YI-10LF
Manufacturer:
IDT
Quantity:
20 000
Company:
Part Number:
ICS1893YI-10LFT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
ICS1893 Rev C 6/6/00
Table 2-1.
Signal references
Symbols
Terms:
‘ set’ ,
‘ active’ ,
‘ asserted’ ,
Terms:
‘ cleared’ ,
‘ de-asserted’ ,
‘ inactive’
Terms:
‘ twisted-pair receiver’
Terms:
‘ twisted-pair transmitter’
ICS1893 Data Sheet - Release
Item
Conventions and Nomenclature (Continued)
The terms ‘ set’ , ‘ active’ , and ‘ asserted’ are synonymous.
They do not necessarily infer logic one.
(For example, an active-low signal can be set to logic zero.)
The terms ‘ cleared’ , ‘ inactive’ , and ‘ de-asserted’ are synonymous.
They do not necessarily infer logic zero.
In reference to the ICS1893, the term ‘ Twisted-Pair Receiver’ refers to the set
of Twisted-Pair Receive output pins (TP_RXP and TP_RXN).
In reference to the ICS1893, the term ‘ Twisted-Pair Transmitter’ refers to the
set of Twisted-Pair Transmit output pins (TP_TXP and TP_TXN).
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
•
•
•
•
When referring to signals, the terms:
– ‘ FALSE’ , ‘ low’ , or ‘ zero’ represent signals that are logic zero.
– ‘ TRUE’ , ‘ high’ , or ‘ one’ represent signals that are logic one.
Chapter 10, “ DC and AC Operating Conditions”
specifications for ‘ logic zero’ and ‘ logic one’ signals.
In this data sheet, code group names are referred to as ‘ symbols’ and they
are shown between '/' (slashes). For example, the symbol /J/ represents
the first half of the Start-of-Stream Delimiter (SSD1).
Symbol sequences are shown in succession. For example, /I/J/K/
represents an IDLE followed by the SSD.
14
Convention / Nomenclature
Chapter 2 Conventions and Nomenclature
defines the electrical
June, 2000