ICS1893YI-10LF IDT, Integrated Device Technology Inc, ICS1893YI-10LF Datasheet - Page 93
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ICS1893YI-10LF
Manufacturer Part Number
ICS1893YI-10LF
Description
PHYCEIVER LOW PWR 3.3V 64-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
PHYceiver™r
Type
PHY Transceiverr
Specifications of ICS1893YI-10LF
Protocol
MII
Voltage - Supply
3.14 V ~ 3.47 V
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Lead Free Status / Rohs Status
Compliant
Other names
1893YI-10LF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICS1893YI-10LF
Manufacturer:
IDT
Quantity:
390
Company:
Part Number:
ICS1893YI-10LF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
ICS1893YI-10LF
Manufacturer:
IDT
Quantity:
20 000
Company:
Part Number:
ICS1893YI-10LFT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
8.12.3 Auto-Negotiation Progress Monitor (bits 17.13:11)
8.12.4 100Base-TX Receive Signal Lost (bit 17.10)
ICS1893 Rev C 6/6/00
The Auto-Negotiation Progress Monitor consists of the Auto-Negotiation Complete bit (bit 17.4) and the
three Auto-Negotiation Monitor bits (bits 17.13:11). The Auto-Negotiation Progress Monitor continually
examines the state of the Auto-Negotiation Process State Machine and reports the status of
Auto-Negotiation using the three Auto-Negotiation Monitor bits. Therefore, the value of these three bits
provides the status of the Auto-Negotiation Process.
These three bits are initialized to logic zero in one of the following ways:
•
•
•
If Auto-Negotiation is enabled, these bits continually latch the highest state that the Auto-Negotiation State
Machine achieves. That is, they are updated only if the binary value of the next state is greater than the
binary value of the present state as outlined in
Note:
Table 8-19.
The 100Base-TX Receive Signal Lost bit indicates to an STA whether the ICS1893 has lost its 100Base-TX
Receive Signal. If this bit is set to a logic:
•
•
This bit is a latching high bit. (For more information on latching high and latching low bits, see
8.1.4.1, “ Latching High Bits”
Note:
Auto-Negotiation State Machine
Idle
Parallel Detected
Parallel Detection Failure
Ability Matched
Acknowledge Match Failure
Acknowledge Matched
Consistency Match Failure
Consistency Matched
Auto-Negotiation Completed
Successfully
A reset (see
Disabling Auto-Negotiation [see
Restarting Auto-Negotiation [see
Zero, it indicates the Receive Signal has remained valid since either the last read or reset of this register.
One, it indicates the Receive Signal was lost since either the last read or reset of this register.
ICS1893 - Release
An MDIO read of these bits provides a history of the greatest progress achieved by the
auto-negotiation process. In addition, the MDIO read latches the present state of the
Auto-Negotiation State Machine for a subsequent read.
This bit has no definition in 10Base-T mode.
Auto-Negotiation State Machine (Progress Monitor)
Section 5.1, “ Reset Operations”
and
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
Section 8.1.4.2, “ Latching Low Bits”
Section 8.2.4, “ Auto-Negotiation Enable (bit 0.12)”
Section 8.2.7, “ Restart Auto-Negotiation (bit 0.9)”
Complete Bit
Negotiation
(Bit 17.4)
Auto-
0
0
0
0
0
0
0
0
1
Table
)
93
Auto-Negotiation Progress Monitor
8-19.
Monitor Bit 2
Negotiation
(Bit 17.13)
Auto-
0
0
0
0
1
1
1
1
0
.)
Monitor Bit 1
Chapter 8 Management Register Set
Negotiation
(Bit 17.12)
Auto-
0
0
1
1
0
0
1
1
0
]
]
Monitor Bit 0
Negotiation
(Bit 17.11)
Auto-
0
1
0
1
0
1
0
1
0
Section
June, 2000