ICS1893YI-10LF IDT, Integrated Device Technology Inc, ICS1893YI-10LF Datasheet - Page 88
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ICS1893YI-10LF
Manufacturer Part Number
ICS1893YI-10LF
Description
PHYCEIVER LOW PWR 3.3V 64-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
PHYceiver™r
Type
PHY Transceiverr
Specifications of ICS1893YI-10LF
Protocol
MII
Voltage - Supply
3.14 V ~ 3.47 V
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Lead Free Status / Rohs Status
Compliant
Other names
1893YI-10LF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICS1893YI-10LF
Manufacturer:
IDT
Quantity:
390
Company:
Part Number:
ICS1893YI-10LF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
ICS1893YI-10LF
Manufacturer:
IDT
Quantity:
20 000
Company:
Part Number:
ICS1893YI-10LFT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
8.11 Register 16: Extended Control Register
ICS1893 Rev C 6/6/00
Table 8-16
customize the operations of the device.
Note:
1. For an explanation of acronyms used in
2. During any write operation to any bit in this register, the STA must write the default value to all
Table 8-16.
† The default is the state of this pin at reset.
16.15
16.14
16.13
16.12
16.11
16.10
16.9
16.8
16.7
16.6
16.5
16.4
16.3
16.2
16.1
16.0
Bit
Reserved bits.
ICS1893 Data Sheet - Release
Command Override Write
enable
ICS reserved
ICS reserved
ICS reserved
ICS reserved
PHY Address Bit 4
PHY Address Bit 3
PHY Address Bit 2
PHY Address Bit 1
PHY Address Bit 0
Stream Cipher Test Mode Normal operation
ICS reserved
NRZ/NRZI encoding
Transmit invalid codes
ICS reserved
Stream Cipher disable
lists the bits for the Extended Control Register, which the ICS1893 provides to allow an STA to
Extended Control Register (register 16 [0x10])
Definition
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
Disabled
Read unspecified
Read unspecified
Read unspecified
Read unspecified
For a detailed explanation of this bit’ s operation,
see
For a detailed explanation of this bit’ s operation,
see
For a detailed explanation of this bit’ s operation,
see
For a detailed explanation of this bit’ s operation,
see
For a detailed explanation of this bit’ s operation,
see
Read unspecified
NRZ encoding
Disabled
Read unspecified
Stream Cipher enabled Stream Cipher disabled
Section 6.8, “ Status Interface”
Section 6.8, “ Status Interface”
Section 6.8, “ Status Interface”
Section 6.8, “ Status Interface”
Section 6.8, “ Status Interface”
When Bit = 0
Table
88
8-16, see
Enabled
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Test mode
Read unspecified
NRZI encoding
Enabled
Read unspecified
When Bit = 1
Chapter 1, “ Abbreviations and Acronyms”
.
.
.
.
.
Chapter 8 Management Register Set
RW/0
RW/0
RW/0
RW/0
RW/0
RW/0
cess
RW
RW
RW
RW
RW
Ac-
RO
RO
RO
RO
RO
SC
SF
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
P4RD†
P3TD†
P0AC†
P1CL†
P2LI†
fault
De-
0
0
0
0
0
0
–
1
0
0
0
June, 2000
Hex
.
–
–
–
8