PIC24EP64MC204-E/PT Microchip Technology, PIC24EP64MC204-E/PT Datasheet - Page 103

• Manufacturer Part Number: PIC24EP64MC204-E/PT
• Description: 16 Bit MCU, 64KB Flash, 8KB RAM, 60 MHz, 44 Pin, MCPWM,QEI, 3 OpAmp, 4 Comp, PTG
• Manufacturer: Microchip Technology

4.4.1
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X,
extends the available data space through a paging
scheme, which allows the available data space to be
accessed using MOV instructions in a linear fashion
for pre- and post-modified effective addresses (EA).
The upper half of base data space address is used
in conjunction with the data space page registers,
the 10-bit read page register (DSRPAG) or the 9-bit
write page register (DSWPAG), to form an extended
data space (EDS) address or Program Space
Visibility (PSV) address. The data space page
registers are located in the SFR space.
EXAMPLE 4-1:
 2011-2012 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
and
Note: DS read access when DSRPAG = 0x000 will force an Address Error trap.
PAGED MEMORY SCHEME
PIC24EPXXXGP/MC20X
(DSRPAG = don't care)
EXTENDED DATA SPACE (EDS) READ ADDRESS GENERATION
EA<15> = 0
PSV address
Generate
architecture
0
DSRPAG
DSRPAG<8:0>
Select
No EDS access
Y
DSRPAG<9>
DSRPAG<9>
9 bits
N
= 1?
24-bit EDS EA
Construction of the EDS address is shown in
Figure
bit EA<15> = 1, DSRPAG<8:0> is concatenated onto
EA<14:0> to form the 24-bit EDS read address.
Similarly
DSWPAG<8:0> is concatenated onto EA<14:0> to
form the 24-bit EDS write address.
EA<15>
0
1
4-1. When DSRPAG<9> = 0 and base address
when
16-bit DS EA
15 bits
EA
EA
base
address
Select
Byte
Select
Byte
DS70657F-page 103
bit
EA<15> = 1,