PIC24EP64MC204-E/PT Microchip Technology, PIC24EP64MC204-E/PT Datasheet - Page 177

• Manufacturer Part Number: PIC24EP64MC204-E/PT
• Description: 16 Bit MCU, 64KB Flash, 8KB RAM, 60 MHz, 44 Pin, MCPWM,QEI, 3 OpAmp, 4 Comp, PTG
• Manufacturer: Microchip Technology

11.4.4.2
In contrast to inputs, the outputs of the peripheral pin
select options are mapped on the basis of the pin. In
this case, a control register associated with a particular
pin dictates the peripheral output to be mapped. The
RPORx registers are used to control output mapping.
Like the RPINRx registers, each register contains sets
of 6 bit fields, with each set associated with one RPn
pin (see
value of the bit field corresponds to one of the periph-
erals, and that peripheral’s output is mapped to the pin
(see
A null output is associated with the output register reset
value of ‘0’. This is done to ensure that remappable out-
puts remain disconnected from all output pins by
default.
TABLE 11-3:
 2011-2012 Microchip Technology Inc.
DEFAULT PORT
U1TX
U2TX
SDO2
SCK2
SS2
C1TX
OC1
OC2
OC3
OC4
C1OUT
C2OUT
C3OUT
SYNCO1
QEI1CCMP
REFCLKO
C4OUT
Note 1:
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
Table 11-3
(2)
2:
Function
Register 11-18
(1)
This function is available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
This function is available in dsPIC33EPXXXGP/MC50X devices only.
(1)
Output Mapping
and
OUTPUT SELECTION FOR REMAPPABLE PINS (RPn)
Figure
through
11-3).
RPnR<5:0>
Register
000000
000001
000011
001000
001001
001010
001110
010000
010001
010010
010011
011000
011001
011010
101101
101111
110001
110010
11-27). The
RPn tied to default pin
RPn tied to UART1 transmit
RPn tied to UART2 transmit
RPn tied to SPI2 data output
RPn tied to SPI2 clock output
RPn tied to SPI2 slave select
RPn tied to CAN1 transmit
RPn tied to Output Compare 1 output
RPn tied to Output Compare 2 output
RPn tied to Output Compare 3 output
RPn tied to Output Compare 4 output
RPn tied to Comparator Output 1
RPn tied to Comparator Output 2
RPn tied to Comparator Output 3
RPn tied to PWM primary time base sync output
RPn tied to QEI 1 counter comparator output
RPn tied to Reference Clock output
RPn tied to Comparator Output 4
FIGURE 11-3:
11.4.4.3
The control schema of the peripheral select pins is not
limited to a small range of fixed peripheral configura-
tions. There are no mutual or hardware-enforced lock-
outs between any of the peripheral mapping SFRs.
Literally any combination of peripheral mappings
across any or all of the RPn pins is possible. This
includes both many-to-one and one-to-many mappings
of peripheral inputs and outputs to pins. While such
mappings may be technically possible from a configu-
ration point of view, they may not be supportable from
an electrical point of view.
QEI1CCMP Output
REFCLKO Output
SDO2 Output
U1TX Output
Mapping Limitations
Output Name
Default
MULTIPLEXING REMAPPABLE
OUTPUT FOR RPn
RPnR<5:0>
48
49
0
1
2
Output Data
DS70657F-page 177
RPn