PIC24EP64MC204-E/PT Microchip Technology, PIC24EP64MC204-E/PT Datasheet - Page 171

• Manufacturer Part Number: PIC24EP64MC204-E/PT
• Description: 16 Bit MCU, 64KB Flash, 8KB RAM, 60 MHz, 44 Pin, MCPWM,QEI, 3 OpAmp, 4 Comp, PTG
• Manufacturer: Microchip Technology

11.0
Many of the device pins are shared among the
peripherals and the parallel I/O ports. All I/O input ports
feature Schmitt Trigger inputs for improved noise
immunity.
11.1
Generally, a parallel I/O port that shares a pin with a
peripheral is subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
FIGURE 11-1:
 2011-2012 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
2: Some registers and associated bits
I/O PORTS
Parallel I/O (PIO) Ports
of
dsPIC33EPXXXMC20X/50X,
PIC24EPXXXGP/MC20X
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer
(DS70598) of the “dsPIC33E/PIC24E
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
Read Port
Read LAT
Read TRIS
Data Bus
WR TRIS
WR LAT +
WR Port
to
the
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Section
Peripheral Output Enable
Peripheral Output Data
Peripheral Input Data
Peripheral Module Enable
Peripheral Module
dsPIC33EPXXXGP50X,
PIO Module
TRIS Latch
Data Latch
10.
D
D
CK
CK
“I/O
Q
families
Q
Ports”
and
of
in
Output Multiplexers
has ownership of the output data and control signals of
the I/O pin. The logic also prevents “loop through,” in
which a port’s digital output can drive the input of a
peripheral that shares the same pin.
illustrates how ports are shared with other peripherals
and the associated I/O pin to which they are connected.
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
can be read, but the output driver for the parallel port bit
is disabled. If a peripheral is enabled, but the peripheral
is not actively driving a pin, that pin can be driven by a
port.
All port pins have eight registers directly associated
with their operation as digital I/O. The data direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is a ‘1’, then the pin
is an input. All port pins are defined as inputs after a
Reset. Reads from the latch (LATx) read the latch.
Writes to the latch write the latch. Reads from the port
(PORTx) read the port pins, while writes to the port pins
write the latch.
Any bit and its associated data and control registers
that are not valid for a particular device is disabled.
This means the corresponding LATx and TRISx
registers and the port pin are read as zeros.
When a pin is shared with another peripheral or
function that is defined as an input only, it is
nevertheless regarded as a dedicated port because
there is no other competing source of outputs.
1
0
1
0
Output Enable
Output Data
Input Data
I/O
I/O Pin
DS70657F-page 171
Figure 11-1