PIC24EP64MC204-E/PT Microchip Technology, PIC24EP64MC204-E/PT Datasheet - Page 144

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PIC24EP64MC204-E/PT

Manufacturer Part Number
PIC24EP64MC204-E/PT
Description
16 Bit MCU, 64KB Flash, 8KB RAM, 60 MHz, 44 Pin, MCPWM,QEI, 3 OpAmp, 4 Comp, PTG
Manufacturer
Microchip Technology
Datasheet

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Part Number:
PIC24EP64MC204-E/PT
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
REGISTER 8-7:
REGISTER 8-8:
DS70657F-page 144
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
Note 1:
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13-0
Note 1:
R/W-0
R/W-0
R/W-0
U-0
2:
If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
The number of DMA transfers = CNT<13:0> + 1.
PAD<15:0>: Peripheral Address Register bits
Unimplemented: Read as ‘0’
CNT<13:0>: DMA Transfer Count Register bits
R/W-0
R/W-0
R/W-0
U-0
DMA
DMA
X
X
PAD: DMA CHANNEL
CNT: DMA CHANNEL
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CNT<7:0>
PAD<15:8>
PAD<7:0>
X
X
TRANSFER COUNT REGISTER
PERIPHERAL ADDRESS REGISTER
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
‘0’ = Bit is cleared
R/W-0
R/W-0
R/W-0
R/W-0
(2)
(2)
CNT<13:8>
R/W-0
R/W-0
R/W-0
R/W-0
(2)
 2011-2012 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
R/W-0
R/W-0
R/W-0
R/W-0
(1)
(1)
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
bit 0
bit 8
bit 0

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