PIC24EP64MC204-E/PT Microchip Technology, PIC24EP64MC204-E/PT Datasheet - Page 361

• Manufacturer Part Number: PIC24EP64MC204-E/PT
• Description: 16 Bit MCU, 64KB Flash, 8KB RAM, 60 MHz, 44 Pin, MCPWM,QEI, 3 OpAmp, 4 Comp, PTG
• Manufacturer: Microchip Technology

REGISTER 25-3:
 2011-2012 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-10
bit 9
bit 8
bit 7-6
Note 1:
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
R/W-0
R/W-0
CON
EVPOL<1:0>
Inputs that are selected and not available will be tied to V
inputs for each package.
CON: Comparator Enable bit
1 = Comparator is enabled
0 = Comparator is disabled
COE: Comparator Output Enable bit
1 = Comparator output is present on the CxOUT pin
0 = Comparator output is internal only
CPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
Unimplemented: Read as ‘0’
CEVT: Comparator Event bit
1 = Comparator event according to EVPOL<1:0> settings occurred; disables future triggers and
0 = Comparator event did not occur
COUT: Comparator Output bit
When CPOL = 0 (non-inverted polarity):
1 = V
0 = V
When CPOL = 1 (inverted polarity):
1 = V
0 = V
EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits
11 = Trigger/Event/Interrupt generated on any change of the comparator output (while CEVT = 0)
10 = Trigger/Event/Interrupt generated only on high to low transition of the polarity-selected
01 = Trigger/Event/Interrupt generated only on low to high transition of the polarity-selected
00 = Trigger/Event/Interrupt generation is disabled
R/W-0
R/W-0
interrupts until the bit is cleared
COE
IN
IN
IN
IN
comparator output (while CEVT = 0)
High-to-low transition of the comparator output
comparator output (while CEVT = 0)
If CPOL = 1 (inverted polarity):
Low-to-high transition of the comparator output
If CPOL = 0 (non-inverted polarity):
If CPOL = 1 (inverted polarity):
High-to-low transition of the comparator output
If CPOL = 0 (non-inverted polarity):
Low-to-high transition of the comparator output
CM4CON: COMPARATOR CONTROL REGISTER
+ > V
+ < V
+ < V
+ > V
IN
IN
IN
IN
-
-
-
-
W = Writable bit
‘1’ = Bit is set
R/W-0
CPOL
U-0
—
R/W-0
CREF
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
SS
. See the
U-0
U-0
“Pin Diagrams”
—
—
x = Bit is unknown
R/W-0
R/W-0
CEVT
section for available
CCH<1:0>
DS70657F-page 361
R/W-0
COUT
R/W-0
bit 8
bit 0